Instruction Manual

52 www.xilinx.com XUP Virtex-II Pro Development System
UG069 (v1.0) March 8, 2005
Chapter 2: Using the System
R
39 EXP_IO_74 W7 J6.32 LVTTL
41 EXP_IO_75 W8 J6.35 LVTTL
43 EXP_IO_76 AB3 J6.34 –v
45 EXP_IO_77 AB4
47 EXP_IO_78 AB2
49 EXP_IO_79 AC2
51
VCC3V3 J5.3 J6.3
53
VCC3V3 J5.3 J6.3
55
VCC3V3 J5.3 J6.3
57
VCC5V0 J5.2 J6.2
59
VCC5V0 J5.2 J6.2
2 GND J5.1 J6.1
4 GND J5.1 J6.1
6 GND J5.1 J6.1
8 GND J5.1 J6.1
10 GND J5.1 J6.1
12 GND J5.1 J6.1
14 GND J5.1 J6.1
16 GND J5.1 J6.1
18 GND J5.1 J6.1
20 GND J5.1 J6.1
22 GND J5.1 J6.1
24 GND J5.1 J6.1
26 GND J5.1 J6.1
28 GND J5.1 J6.1
30 GND J5.1 J6.1
32 GND J5.1 J6.1
34 GND J5.1 J6.1
36 GND J5.1 J6.1
38 GND J5.1 J6.1
40 GND J5.1 J6.1
Table 2-13: Bottom Expansion Header Pinout (Continued)
J4
Pin
Signal
FPGA
Pin
Digilent
EXP Pin
IO Type