Instruction Manual

XUP Virtex-II Pro Development System www.xilinx.com 47

UG069 (v1.0) March 8, 2005

Using the Expansion Headers and Digilent Expansion Connectors

48 GND – J5.1 J6.1 –

50 GND – J5.1 J6.1 –

52 GND – J5.1 J6.1 –

54 GND – J5.1 J6.1 –

56 GND – J5.1 J6.1 –

58 GND – J5.1 J6.1 –

60 GND – J5.1 J6.1 –

Table 2-11: Upper Middle Expansion Header Pinout

J2|

Signal

FPGA

Digilent

EXP Pin

IO Type

VCC5V0 – J5.2 J6.2 –

VCC3V3 – J5.3 J6.3 –

11 EXP_IO_20 P8 J5.16 LVTTL

13 EXP_IO_21 P7 J5.17 LVTTL

15 EXP_IO_22 N4 J5.18 LVTTL

17 EXP_IO_23 N3 J5.19 LVTTL

19 EXP_IO_24 P3 J5.20 LVTTL

21 EXP_IO_25 P2 J5.21 LVTTL

23 EXP_IO_26 R8 J5.22 LVTTL

25 EXP_IO_27 R7 J5.23 LVTTL

27 EXP_IO_28 P5 J5.24 LVTTL

29 EXP_IO_29 P4 J5.25 LVTTL

31 EXP_IO_30 R2 J5.26 LVTTL

33 EXP_IO_31 T2 J5.27 LVTTL

35 EXP_IO_32 R6 J5.28 LVTTL

37 EXP_IO_33 R5 J5.29 LVTTL

39 EXP_IO_34 R4 J5.30 LVTTL

41 EXP_IO_35 R3 J5.31 LVTTL

Table 2-10: Top Expansion Header Pinout (Continued)

Signal

FPGA

Digilent

EXP Pin

I/O Type