Instruction Manual

XUP Virtex-II Pro Development System www.xilinx.com 29

UG069 (v1.0) March 8, 2005

Using the DIMM Module DDR SDRAM

The Xilinx PLB DDR SDRAM controller is a soft IP core designed for Xilinx FPGAs that

support different CAS latencies and memory data widths set by design parameters.

The DDR SDRAM controller logic instantiates DDR input and output registers on the

address, data, and control signals, so the clock to output delays match the clock output

delay. The DDR SDRAM clocking structure as shown in Figure 2-10 is a simplified version

of the clocking structure mentioned in DS425

Figure 2-10: Clock Generation for the DDR SDRAM

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