Instruction Manual

ManualsBrandsDigilent ManualsHardware6003-410-000P-KIT

Xilinx University Program

Virtex-II Pro Development

System

Hardware Reference Manual

UG069 (v1.0) March 8, 2005

Summary of content (138 pages)

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Xilinx University Program Virtex-II Pro Development System Hardware Reference Manual UG069 (v1.
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R "Xilinx" and the Xilinx logo shown above are registered trademarks of Xilinx, Inc. Any rights not expressly granted herein are reserved. CoolRunner, RocketChips, Rocket IP, Spartan, StateBENCH, StateCAD, Virtex, XACT, XC2064, XC3090, XC4005, and XC5210 are registered trademarks of Xilinx, Inc. The shadow X shown above is a trademark of Xilinx, Inc. ACE Controller, ACE Flash, A.K.A.
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Contents Chapter 1: XUP Virtex-II Pro Development System Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Board Components . . . . . . . . . .
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Appendix A: Configuring the FPGA from the Embedded USB Configuration Port Appendix B: Programming the Platform FLASH PROM User Area Appendix C: Restoring the Golden FPGA Configuration Appendix D: Using the Golden FPGA Configuration for System SelfTest Hardware-Based Tests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Power Supply and RESET Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Appendix E: User Constraint Files (UCF) Appendix F: Links to the Component Data Sheets FPGA Related Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DDR SDRAM Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Audio Processing . . . . . . . . . . . . . . . . . . . .
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XUP Virtex-II Pro Development System www.xilinx.com UG069 (v1.
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Figures Chapter 1: XUP Virtex-II Pro Development System Figure 1-1: XUP Virtex-II Pro Development System Block Diagram . . . . . . . . . . . . . . . . . 14 Figure 1-2: XUP Virtex-II Pro Development System Board Photo. . . . . . . . . . . . . . . . . . . . 15 Figure 1-3: I/O Bank Connections to Peripheral Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Chapter 2: Using the System Figure 2-1: Typical Switching Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Figure A-8: Programming the FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Appendix B: Programming the Platform FLASH PROM User Area Figure B-1: Operation Mode Selection: Prepare Configuration Files . . . . . . . . . . . . . . . . . 77 Figure B-2: Selecting PROM File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Figure B-3: Selecting a PROM with Design Revisioning Enabled . . . . . . . . . . . . . . . .
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Figure D-11: Specifying IP Address for XUP Virtex-II Pro Development System . . . . . 107 Figure D-12: Web Server Running . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Figure D-13: Web Server Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Figure D-14: Web Server Stopped . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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XUP Virtex-II Pro Development System www.xilinx.com UG069 (v1.
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Tables Chapter 1: XUP Virtex-II Pro Development System Table 1-1: XC2VP20 and XC2VP30 Device Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Chapter 2: Using the System Table 2-1: System Configuration Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 2-2: Clock Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 2-3: SPD EEPROM Contents . . . . . . . . . . . . . . .
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Appendix A: Configuring the FPGA from the Embedded USB Configuration Port Appendix B: Programming the Platform FLASH PROM User Area Appendix C: Restoring the Golden FPGA Configuration Appendix D: Using the Golden FPGA Configuration for System SelfTest Appendix E: User Constraint Files (UCF) Appendix F: Links to the Component Data Sheets XUP Virtex-II Pro Development System www.xilinx.com UG069 (v1.
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R Chapter 1 XUP Virtex-II Pro Development System Features • Virtex™-II Pro FPGA with PowerPC™ 405 cores • Up to 2 GB of Double Data Rate (DDR) SDRAM • System ACE™ controller and Type II CompactFlash™ connector for FPGA configuration and data storage • Embedded Platform Cable USB configuration port • High-speed SelectMAP FPGA configuration from Platform Flash In-System Programmable Configuration PROM • Support for “Golden” and “User” FPGA configuration bitstreams • On-board 10/100 Ethernet PHY
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R Chapter 1: XUP Virtex-II Pro Development System General Description The XUP Virtex-II Pro Development System provides an advanced hardware platform that consists of a high performance Virtex-II Pro Platform FPGA surrounded by a comprehensive collection of peripheral components that can be used to create a complex system and to demonstrate the capability of the Virtex-II Pro Platform FPGA. Block Diagram Figure 1-1 shows a block diagram of the XUP Virtex-II Pro Development System.
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R General Description Figure 1-2: XUP Virtex-II Pro Development System Board Photo Virtex-II Pro FPGA U1 is a Virtex-II Pro FPGA device packaged in a flip-chip-fine-pitch FF896 BGA package. Two different capacity FPGAs can be used on the XUP Virtex-II Pro Development System with no change in functionality. Table 1-1 lists the Virtex-II Pro device features.
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R Chapter 1: XUP Virtex-II Pro Development System Table 1-1: XC2VP20 and XC2VP30 Device Features (Continued) Features XC2VP20 XC2VP30 1584 Kb 2448 Kb DCMs 8 8 PowerPC RISC Cores 2 2 Multi-Gigabit Transceivers 8 8 Block RAMs Figure 1-3 identifies the I/O banks that are used to connect the various peripheral devices to the FPGA. SXGA port 256M x 64/72 DDR SDRAM DIMM MODULE AC97 Audio 10/100 Ethernet OVER VOLTAGE CLAMPS EXPANSION CONNECTORS 1 0 2 7 3 6 4 5 3.
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R General Description Multi-Gigabit Transceivers Four of the eight Multi-Gigabit Transceivers (MGTs) that are present in the Virtex-II Pro FPGA are brought out to connectors and can be utilized by the user. Three of the bidirectional MGT channels are terminated at Serial Advanced Technology Attachment (SATA) connectors and the fourth channel terminates at user-supplied Sub-Miniature A (SMA) connectors.
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R Chapter 1: XUP Virtex-II Pro Development System User LEDs, Switches, and Push Buttons A total of four LEDs are provided for user-defined purposes. When the FPGA drives a logic 0, the corresponding LED turns on. A single four-position DIP switch and five push buttons are provided for user input. If the DIP switch is up, closed, or on, or the push button is pressed, a logic 0 is seen by the FPGA, otherwise a logic 1 is indicated.
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R Chapter 2 Using the System Configuring the Power Supplies The XUP Virtex-II Pro Development System supports the independent creation of the power supplies for the core voltage of 1.5V (FPGA_VINT), 2.5V general-purpose power, I/O and/or VCCAUX supplies (VCC2V5), and 3.3V I/O and general-purpose power (VCC3V3). These voltages are created by synchronous buck-switching regulators derived from the 4.5V-5.
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R Chapter 2: Using the System Because of the analog nature of the MGTs, the power for those elements are created by low noise, low dropout linear regulators. Figure 2-2 shows the power supply for the MGTs. U20 FIXED 2.5V LDO 2 VCC3V3 1 C429 5 + 33OUF 6.3V IN OUT SHDN GND SENSE TAB 4 VCC_MGT 3 C427 6 + C428 330UF 6.3V 1000PF C430 LT1963AEQ-25 0.1UF U21 C431 FIXED 2.5V LDO + 2 33OUF 6.3V 1 5 IN OUT SHDN GND SENSE TAB 4 VTT_MGT 3 6 LT1963AEQ-25 C432 + C433 1000PF 330UF 6.
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R Configuring the FPGA The Platform Flash is normally disabled after the FPGA is finished configuring and has asserted the DONE signal. If additional data is made available to the FPGA after the completion of configuration, jumper JP9 must be moved from the NORMAL to the EXTENDED position to permanently enable the PROM and allow the FPGA to clock out the additional data using the FPGA_PROM_CLOCK signal.
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R Chapter 2: Using the System & CPLD JTAG Port Test JTAG Port SystemACE PLATFORM FLASH GOLDEN VERSION SELECT USER Config JTAG Port Micro Port USB2 Microcontroller JTAG Port Figure 2-3 illustrates the configuration data path.
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R Clock Generation and Distribution Table 2-1: System Configuration Status LEDs (Continued) LED Status System Status D19 (Green) PROM Config D20 (Green) CF Config D14 (Amber) GOLDEN Config D4 (Red) Done JTAG USB or PC4 LOADING OFF ON OFF OFF JTAG USB or PC4 COMPLETED OFF ON OFF ON Clock Generation and Distribution The XUP Virtex-II Pro Development System supports six clock sources: • A 100 MHz system clock (Y2), • A 75 MHz clock (U10) for the MGTs operating the Serial Advanced Technolog
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R Chapter 2: Using the System Figure 2-4: External Differential Clock Inputs The alternate clock input is obtained from a user-supplied 3.3V oscillator. The footprint on the printed circuit board supports either a full size (21mm x 13mm) or half size (13mm x 13mm) through-hole oscillator. Figure 2-5 identifies the location of the alternate clock input oscillator.
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R Using the DIMM Module DDR SDRAM Read and Write accesses to the DDR SDRAM are burst oriented: accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an Active command, which is followed by a Read or Write command. The address bits registered coincident with the Read or Write command are used to select the bank and starting column location for the burst address.
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R Chapter 2: Using the System SCL FROM MASTER 1 2 8 9 SDA OUTPUT FROM TRANSMITTER SDA OUTPUT FROM RECEIVER START BIT ACKNOWLEDGE UG069_08_021405 Figure 2-7: Acknowledge Response from Receiver The SPD device always responds with an acknowledge after recognition of a start condition and its slave address (100). If a read command was issued, the SPD device transmits eight bits of data, releases the SDRAM_SDA data line, and monitors the SDRAM_SDA data line for an acknowledge.
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R Using the DIMM Module DDR SDRAM The ability to read the SPD EEPROM is important because the module specific timing parameters are included in the EEPROM data and are required by the DDR SDRAM controller to provide the highest memory throughput. The definitions of the SPD data bytes are outlined in Table 2-3.
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R Chapter 2: Using the System Table 2-3: SPD EEPROM Contents (Continued) Byte Description 29 Minimum RAS# to CAS# delay (trcd) 30 Minimum RAS# pulse width (tras) 31 Module rank density 32 Command and address setup time (tas, tcms) 33 Command and address hold time (tah, tcmh) 34 Data setup time (tds) 35 Data hold time (tdh) 36-40 Reserved 41 Minimum ACTIVE/AUTO REFRESH time 42 Minimum AUTO REFRESH to ACTIVE/AUTO REFRESH command period 43 Max cycle time 44 Max DQS-DQ skew 45 Max
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R Using the DIMM Module DDR SDRAM The Xilinx PLB DDR SDRAM controller is a soft IP core designed for Xilinx FPGAs that support different CAS latencies and memory data widths set by design parameters. The DDR SDRAM controller logic instantiates DDR input and output registers on the address, data, and control signals, so the clock to output delays match the clock output delay. The DDR SDRAM clocking structure as shown in Figure 2-10 is a simplified version of the clocking structure mentioned in DS425.
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R Chapter 2: Using the System Xilinx has qualified several different types of PC2100 memory modules for use in the XUP Virtex-II Pro Development System. These modules cover various densities, organizations, and features. The qualified memory modules are identified in Table 2-4. For an updated list of supported modules, consult the XUP Virtex-II Pro Development System support Web site at: http://www.xilinx.com/univ/xupv2p.
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R Using the DIMM Module DDR SDRAM Table 2-5: DDR SDRAM Connections (Continued) Direction DIMM Module Pin FPGA Pin I/O Type SDRAM_DQ[8] I/O 12 J26 SSTL2-II SDRAM_DQ[9] I/O 13 G27 SSTL2-II SDRAM_DQ[10] I/O 19 G28 SSTL2-II SDRAM_DQ[11] I/O 20 G30 SSTL2-II SDRAM_DQ[12] I/O 105 L23 SSTL2-II SDRAM_DQ[13] I/O 106 L24 SSTL2-II SDRAM_DQ[14] I/O 109 H27 SSTL2-II SDRAM_DQ[15] I/O 110 H28 SSTL2-II SDRAM_DQS[1] I/O 14 J29 SSTL2-II SDRAM_DM[1] 0 107 V29 SSTL2-II SD
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R Chapter 2: Using the System Table 2-5: DDR SDRAM Connections (Continued) Direction DIMM Module Pin FPGA Pin I/O Type SDRAM_DQ[33] I/O 55 Y30 SSTL2-II SDRAM_DQ[34] I/O 57 U24 SSTL2-II SDRAM_DQ[35] I/O 60 U23 SSTL2-II SDRAM_DQ[36] I/O 146 V26 SSTL2-II SDRAM_DQ[37] I/O 147 V25 SSTL2-II SDRAM_DQ[38] I/O 150 Y29 SSTL2-II SDRAM_DQ[39] I/O 151 AA29 SSTL2-II SDRAM_DQS[4] I/O 56 V23 SSTL2-II SDRAM_DM[4] 0 149 W28 SSTL2-II SDRAM_DQ[40] I/O 61 Y26 SSTL2-II SDR
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R Using the DIMM Module DDR SDRAM Table 2-5: DDR SDRAM Connections (Continued) Direction DIMM Module Pin FPGA Pin I/O Type SDRAM_DQ[58] I/O 87 AG29 SSTL2-II SDRAM_DQ[59] I/O 88 AD26 SSTL2-II SDRAM_DQ[60] I/O 174 AD25 SSTL2-II SDRAM_DQ[61] I/O 175 AG28 SSTL2-II SDRAM_DQ[62] I/O 178 AH27 SSTL2-II SDRAM_DQ[63] I/O 179 AH29 SSTL2-II SDRAM_DQS[7] I/O 86 AH26 SSTL2-II SDRAM_DM[7] 0 177 W25 SSTL2-II SDRAM_CB[0] I/O 44 R28 SSTL2-II SDRAM_CB[1] I/O 45 U30 SSTL2
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R Chapter 2: Using the System Table 2-5: DDR SDRAM Connections (Continued) Direction DIMM Module Pin FPGA Pin I/O Type SDRAM_A[13] O 167 M23 SSTL2-II SDRAM_CK0 O 137 AC27 SSTL2-II SDRAM_CK0_Z O 138 AC28 SSTL2-II SDRAM_CK1 O 16 AD29 SSTL2-II SDRAM_CK1_Z O 17 AD30 SSTL2-II SDRAM_CK2 O 76 AB23 SSTL2-II SDRAM_CK2_Z O 75 AB24 SSTL2-II CLK_FEEDBACK O – G23 LVCMOS25 CLK_FEEDBACK I – C16 LVCMOS25 SDRAM_CKE0 O 21 R26 SSTL2-II SDRAM_CKE1 O 111 R25 SSTL2-II
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R Using the XSGA Output Design files supplied by Xilinx generate the required timing signals VGA_OUT_BLANK_Z, VGA_HSYNCH, VGA_VSYNCH, and VGA_COMP_SYNCH, as well as memory addressing for bit- and character-mapped display RAM. Charactermapped mode allows for the display of extended ASCII characters in an 8 x 8 pixel block without having to draw the character pixel by pixel. Compile time parameters are passed to the Verilog code that defines the XSGA controller operation.
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VGA_OUT_PIXEL_CLOCK www.xilinx.
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R Using the XSGA Output Table 2-6 lists the Verilog parameter values and the DCM settings for various XSGA output formats. Note: The highlighted settings are exact VESA settings; the others are approximations. Table 2-6: DCM and XSGA Controller Settings for Various XSGA Formats Output Format Pixel Clock DCM Settings Verilog Horizontal Timing Parameters H Active H FP H Synch H BP H Total MHz M D Pixels Pixels Pixels Pixels Pixels 640 x 480 @ 60 Hz 25.
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R Table 2-6: Chapter 2: Using the System DCM and XSGA Controller Settings for Various XSGA Formats (Continued) Output Format Pixel Clock DCM Settings Verilog Horizontal Timing Parameters H Active H FP H Synch H BP H Total MHz M D Pixels Pixels Pixels Pixels Pixels 800 x 600 @ 75 Hz 50.00 1 2 600 1 2 23 626 800 x 600 @ 85 Hz 55.00 11 20 600 1 3 18 622 1024 x 768 @ 60 Hz 65.00 13 20 768 3 6 29 806 1024 x 768 @ 72 Hz 75.
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R Using the AC97 Audio CODEC and Power Amp Table 2-7: XSGA Output Connections (Continued) Direction Video DAC or Output Connector Pin FPGA Pin I/O Type Drive Slew VGA_OUT_GREEN[5] O 7 H11 LVTTL 8 mA SLOW VGA_OUT_GREEN[6] O 8 G11 LVTTL 8 mA SLOW VGA_OUT_GREEN[7] O 9 E11 LVTTL 8 mA SLOW VGA_OUT_BLUE[0] O 16 D15 LVTTL 8 mA SLOW VGA_OUT_BLUE[1] O 17 E15 LVTTL 8 mA SLOW VGA_OUT_BLUE[2] O 18 H15 LVTTL 8 mA SLOW VGA_OUT_BLUE[3] O 19 J15 LVTTL 8 mA SLOW VGA_
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R Chapter 2: Using the System • Independently adjustable input volume controls with mute and a maximum gain of 12 dB and attenuation of 34.5 dB in 1.
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BEEP_TONE_IN 6K8 AUDIO_GND R17 4K7 1UF C33 MONO 1UF MIC_POWER AUDIO_GND R19 47K C34 MIC_IN AUDIO_LINE_IN_LEFT AUDIO_LINE_IN_RIGHT BEEP_TONE 48 AUDIO_GND 270PF C36 SPDIF MONO_OUT PHONE_IN AUX_L AUX_R VIDEO_L VIDEO_R CD_L CD_GND CD_4 MIC2 MIC1 LINE_IN_L LINE_IN_R 42 AVSS1 26 PC_BEEP AUDIO_GND 0.
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Figure 2-13: www.xilinx.
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R Using the LEDs and Switches The FPGA contains the AC97 controller that provides control information and PCM data on the outbound link and receives status information and PCM data in the inbound link. The complete AC97 interface consists of four signals, the clock AC97_BIT_CLOCK, a synchronization pulse AC97_SYNCH, and the two serial data links AC97_SDATA_IN and AC97_SDATA_OUT listed in Table 2-8.
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R Chapter 2: Using the System Table 2-9: User LED and Switch Connections (Continued) Signal Direction FPGA Pin I/O Type Drive Slew PB_LEFT I AH1 LVTTL – – PB_RIGHT I AH2 LVTTL – – Using the Expansion Headers and Digilent Expansion Connectors The XUP Virtex-II Pro Development System allows for four user-supplied expansion headers that are tailored to accept ribbon cables, and two front mounted connectors that are designed to accept Digilent peripheral devices and a single Digilent high-
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R Using the Expansion Headers and Digilent Expansion Connectors In addition to the two low-speed expansion connectors, a single 100-pin high-speed connector is also provided. This connector provides 40 single-ended user I/Os or 34 differential pairs with additional clock resources. These signals are not shared with any other connector. Table 2-17 provides the pinout information.
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R Chapter 2: Using the System Table 2-10: 46 Top Expansion Header Pinout (Continued) J1 Pin Signal FPGA Pin Digilent EXP Pin I/O Type 45 EXP_IO_17 M3 J5.13 LVTTL 47 EXP_IO_18 N1 J5.14 LVTTL 49 EXP_IO_19 P1 J5.15 LVTTL 51 VCC3V3 – J5.3 J6.3 – 53 VCC3V3 – J5.3 J6.3 – 55 VCC3V3 – J5.3 J6.3 – 57 VCC2V5 – – – 59 VCC2V5 – – – 2 GND – J5.1 J6.1 – 4 GND – J5.1 J6.1 – 6 GND – J5.1 J6.1 – 8 GND – J5.1 J6.1 – 10 GND – J5.1 J6.
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R Using the Expansion Headers and Digilent Expansion Connectors Table 2-10: Top Expansion Header Pinout (Continued) J1 Pin Signal FPGA Pin Digilent EXP Pin I/O Type 48 GND – J5.1 J6.1 – 50 GND – J5.1 J6.1 – 52 GND – J5.1 J6.1 – 54 GND – J5.1 J6.1 – 56 GND – J5.1 J6.1 – 58 GND – J5.1 J6.1 – 60 GND – J5.1 J6.1 – Table 2-11: Upper Middle Expansion Header Pinout J2| Pin Signal FPGA Pin Digilent EXP Pin IO Type 1 VCC5V0 – J5.2 J6.2 – 3 VCC5V0 – J5.2 J6.
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R Chapter 2: Using the System Table 2-11: 48 Upper Middle Expansion Header Pinout (Continued) J2| Pin Signal FPGA Pin Digilent EXP Pin IO Type 43 EXP_IO_36 U1 J5.32 LVTTL 45 EXP_IO_37 V1 J5.33 LVTTL 47 EXP_IO_38 T5 J5.34 LVTTL 49 EXP_IO_39 T6 J5.35 LVTTL 51 VCC3V3 – J5.3 J6.3 – 53 VCC3V3 – J5.3 J6.3 – 55 VCC3V3 – J5.3 J6.3 – 57 VCC5V0 – J5.2 J6.2 – 59 VCC5V0 – J5.2 J6.2 – 2 GND – J5.1 J6.1 – 4 GND – J5.1 J6.1 – 6 GND – J5.1 J6.
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R Using the Expansion Headers and Digilent Expansion Connectors Table 2-11: Upper Middle Expansion Header Pinout (Continued) J2| Pin Signal FPGA Pin Digilent EXP Pin IO Type 46 GND – J5.1 J6.1 – 48 GND – J5.1 J6.1 – 50 GND – J5.1 J6.1 – 52 GND – J5.1 J6.1 – 54 GND – J5.1 J6.1 – 56 GND – J5.1 J6.1 – 58 GND – J5.1 J6.1 – 60 GND – J5.1 J6.
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R Chapter 2: Using the System Table 2-12: 50 Lower Middle Expansion Header Pinout (Continued) J3 Pin Signal FPGA Pin Digilent EXP Pin IO Type 41 EXP_IO_55 Y1 J6.15 LVTTL 43 EXP_IO_56 U7 J6.14 LVTTL 45 EXP_IO_57 U8 J6.17 LVTTL 47 EXP_IO_58 V5 J6.16 LVTTL 49 EXP_IO_59 V6 J6.19 LVTTL 51 VCC3V3 – J5.3 J6.3 – 53 VCC3V3 – J5.3 J6.3 – 55 VCC3V3 – J5.3 J6.3 – 57 VCC2V5 – – – 59 VCC2V5 – – – 2 GND – J5.1 J6.1 – 4 GND – J5.1 J6.1 – 6 GND – J5.
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R Using the Expansion Headers and Digilent Expansion Connectors Table 2-12: Lower Middle Expansion Header Pinout (Continued) J3 Pin Signal FPGA Pin Digilent EXP Pin IO Type 44 GND – J5.1 J6.1 – 46 GND – J5.1 J6.1 – 48 GND – J5.1 J6.1 – 50 GND – J5.1 J6.1 – 52 GND – J5.1 J6.1 – 54 GND – J5.1 J6.1 – 56 GND – J5.1 J6.1 – 58 GND – J5.1 J6.1 – 60 GND – J5.1 J6.
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R Chapter 2: Using the System Table 2-13: 52 Bottom Expansion Header Pinout (Continued) J4 Pin Signal FPGA Pin Digilent EXP Pin IO Type 39 EXP_IO_74 W7 J6.32 LVTTL 41 EXP_IO_75 W8 J6.35 LVTTL 43 EXP_IO_76 AB3 J6.34 –v 45 EXP_IO_77 AB4 – – 47 EXP_IO_78 AB2 – – 49 EXP_IO_79 AC2 – – 51 VCC3V3 – J5.3 J6.3 – 53 VCC3V3 – J5.3 J6.3 – 55 VCC3V3 – J5.3 J6.3 – 57 VCC5V0 – J5.2 J6.2 – 59 VCC5V0 – J5.2 J6.2 – 2 GND – J5.1 J6.1 – 4 GND – J5.1 J6.
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R Using the Expansion Headers and Digilent Expansion Connectors Table 2-13: Bottom Expansion Header Pinout (Continued) J4 Pin Signal FPGA Pin Digilent EXP Pin IO Type 42 GND – J5.1 J6.1 – 44 GND – J5.1 J6.1 – 46 GND – J5.1 J6.1 – 48 GND – J5.1 J6.1 – 50 GND – J5.1 J6.1 – 52 GND – J5.1 J6.1 – 54 GND – J5.1 J6.1 – 56 GND – J5.1 J6.1 – 58 GND – J5.1 J6.1 – 60 GND – J5.1 J6.
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R Chapter 2: Using the System Table 2-14: J5 PIN Signal FPGA Pin Expansion Header Pin IO Type 31 EXP_IO_35 R3 J2.41 LVTTL 33 EXP_IO_37 V1 J2.45 LVTTL 35 EXP_IO_39 T6 J2.49 LVTTL 37 EXP_IO_41 T4 J3.13 LVTTL 39 EXP_IO_43 U3 J3.17 LVTTL 2 VCC5VO – 4 EXP_IO_8 N6 J1.27 LVTTL 6 EXP_IO_10 L5 J1.31 LVTTL 8 EXP_IO_12 M2 J1.35 LVTTL 10 EXP_IO_14 P9 J1.39 LVTTL 12 EXP_IO_16 M4 J1.43 LVTTL 14 EXP_IO_18 N1 J1.47 LVTTL 16 EXP_IO_20 P8 J2.
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R Using the Expansion Headers and Digilent Expansion Connectors Table 2-15: Right Digilent Expansion Connector Pinout (Continued) J5 PIN Signal FPGA Pin Expansion Header Pin IO Type 7 EXP_IO_47 U5 J3.25 LVTTL 9 EXP_IO_49 W2 J3.29 LVTTL 11 EXP_IO_51 U9 J3.33 LVTTL 13 EXP_IO_53 V4 J3.37 LVTTL 15 EXP_IO_55 Y1 J3.41 LVTTL 17 EXP_IO_57 U8 J3.45 LVTTL 19 EXP_IO_59 V6 J3.49 LVTTL 21 EXP_IO_61 AA2 J4.13 LVTTL 23 EXP_IO_63 V8 J4.17 LVTTL 25 EXP_IO_65 W4 J4.
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R Chapter 2: Using the System Table 2-15: J5 PIN Signal FPGA Pin Expansion Header Pin IO Type 30 EXP_IO_72 AA3 J4.35 LVTTL 32 EXP_IO_74 W7 J4.39 LVTTL 34 EXP_IO_74 AB3 J4.
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R Using the Expansion Headers and Digilent Expansion Connectors Table 2-16: High-Speed Digilent Expansion Connector Pinout (Continued) J37 PIN Signal FPGA Pin Differential Pair I/O Type A23 HS_IO_18 AE1 39N_3 LVTTL A24 HS_IO_19 AB6 40P_3 LVTTL A25 HS_IO_20 AB5 40N_3 LVTTL A26 HS_IO_21 Y8 41P_3 LVTTL A27 HS_IO_22 Y7 41N_3 LVTTL A28 HS_IO_23 AD2 42P_3 LVTTL A29 HS_IO_24 AD1 42N_3 LVTTL A30 HS_IO_25 L7 41P_2 LVTTL A31 HS_IO_26 L8 41N_2 LVTTL A32 HS_IO_27
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R Chapter 2: Using the System Table 2-16: High-Speed Digilent Expansion Connector Pinout (Continued) J37 PIN Signal FPGA Pin Differential Pair I/O Type B04 FPGA_TCK – – – B05-B45 GND – – – B46 HS_CLKIN B16 (GCLK6S) No_Pair LVCMOS25 B47 GND – – – B48 HS_CLKIO E3 33P_2 LVTTL B49 VCC5V5 – – – B50 SHIELD – – – Using the CPU Debug Port and CPU Reset The CPU Debug port (J36) is a right angle header that provides connections to the debugging resources of the PowerPC 405
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R Using the CPU Debug Port and CPU Reset Figure 2-15 shows the pinout of the header used to debug the operation of software in the CPU. This is accomplished using debug tools, such as the Xilinx Parallel Cable IV or third party tools. CPU TCK CPU TMS CPU TDI CPU HALT Z CPU TDO 15 1 16 2 CPU TRST GND 3.
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R Chapter 2: Using the System processor reset pulse of 100 microseconds is applied to the PROCESSOR_RESET_Z signal. The RESET_RELOAD circuit is shown in Figure 2-16. ug069_16_021505 Figure 2-16: RELOAD and CPU RESET Circuit Using the Serial Ports Serial ports are useful as simple, low-speed interfaces. These ports can provide communication between a Host machine and a Peripheral machine, or Host-to-Host communications.
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R Using the Serial Ports bit, and odd parity. The data packets are organized differently for mouse and keyboard data. In addition, the keyboard interface supports bidirectional data transfer so the host device can drive the status LEDs on the keyboard. VCC2V5 24 23 14 U28 0.1UF SHDN VCC C446 VL 1 4 5 0.1UF C449 8 RS232_TX_DATA 9 RS232_CTS_OUT 13 RS232_RX_DATA V+ 0.1UF 2.5V RS-232 Transceiver C1- C448 6 C2+ V0.1UF C1- 7 RS232_DSR_OUT 12 RS232_RTS_IN 10 11 0.
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R Chapter 2: Using the System . VCC3V3 BIDIRECTIONAL LEVEL SHIFTER VCC5V0 R108 BSS138 HZ0805E601R-00 3 D 0 L54 HZ0805E601R-00 C441 2 KBD_CLOCK 1 C442 470PF U25 U24 470PF BSS138 3 GND D 3 2 KBD_DATA H CHAH UPPER STACKED_PS2_6PIN GND 3 H CHAH 3K3 J12A L53 R106 2K0 U24 R107 3K3 R105 2K0 GND 0 1 UG069_18_101804 Figure 2-18: PS/2 Serial Port Implementation If no device is actively pulling the signal low, the pull-up resistor pulls up the signal on the FPGA side.
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R Using the Fast Ethernet Network Interface The Ethernet network interface is made up of three distinct components: the Media Access Controller (MAC) contained in the FPGA, a physical layer transceiver (PHY), and the Ethernet coupling magnetics. The LXT972A (U12) is an IEEE 802.3-compliant Fast Ethernet physical layer (PHY) transceiver that supports both 100BASE-TX and 10BASE-T operation. It provides the standard Media Independent Interface (MII) for easy attachment to 10/100 (MACs).
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R Chapter 2: Using the System Figure 2-19 provides a block diagram of the Ethernet interface. FPGA TX_ERROR MAC IP LXT972A TX_ENABLE TX_DATA[3:0] TX_CLOCK RX_CLOCK RX_DATA[3:0] Magnetics RJ-45 RX_ERROR RX_DATA_VALID CARRIER_SENSE COLLISION MDC MDIO UG069_19_012505 Figure 2-19: 10/100 Ethernet Interface Block Diagram The XUP Virtex-II Pro Development System includes a Dallas Semiconductor DS2401P Silicon Serial Number (U13).
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R Using System ACE Controllers for Non-Volatile Storage Table 2-19: 10/100 ETHERNET Connections (Continued) Signal Direction FPGA Pin I/O Type Drive Slew TX_CLOCK I D3 LVTTL – – TX_ENABLE O C4 LVTTL 8 mA SLOW RX_DATA[0] I K6 LVTTL – – RX_DATA[1] I K5 LVTTL – – RX_DATA[2] I J1 LVTTL – – RX_DATA[3] I K1 LVTTL – – RX_DATA_VALID I M7 LVTTL – – RX_ERROR I J2 LVTTL – – RX_CLOCK I M8 LVTTL – – ENET_RESET_Z O G6 LVTTL 8 mA SLOW CARRIER_SENSE I
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R Chapter 2: Using the System configuration, start configuration, select the source of configuration, control the bitstream revision, and reset the device. For the System ACE controller to be properly synchronized with the MPU, the clocks must be synchronized. The clock traces on the XUP Virtex-II Pro Development System that drive the System ACE controller and the MPU interface sections of are matched in length to maintain the required timing relationship.
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R Using the Multi-Gigabit Transceivers Table 2-20: System ACE Connections (Continued) Direction System ACE Pin FPGA Pin I/O Type Drive CF_MPD[3] I/O 62 AF14 LVCMOS25 8 mA CF_MPD[4] I/O 61 AE14 LVCMOS25 8 mA CF_MPD[5] I/O 60 AD14 LVCMOS25 8 mA CF_MPD[6] I/O 59 AC15 LVCMOS25 8 mA CF_MPD[7] I/O 58 AB15 LVCMOS25 8 mA CF_MPD[8] I/O 56 AJ9 LVCMOS25 8 mA CF_MPD[9] I/O 53 AH9 LVCMOS25 8 mA CF_MPD[10] I/O 52 AE10 LVCMOS25 8 mA CF_MPD[11] I/O 51 AE9 LVCMOS25
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R Chapter 2: Using the System The fourth MGT channel pair terminates on user_supplied SMA connectors (J19-22) and can be driven by a user_supplied differential clock input pair, EXTERNAL_CLOCK_P and EXTERNAL_CLOCK_N provided on SMA connectors (J23-24). This EXTERNAL_CLOCK can be used to clock the SATA ports if non-standard signaling rates are required. The MGT connections are shown in Table 2-20. For the user to take advantage of the fourth MGT channel, four SMA connectors must be installed at J19-J22.
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R Using the Multi-Gigabit Transceivers Table 2-21: SATA and MGT Signals (Continued) Signal MGT Location PAD Name I/O Pin Notes SATA_PORT0_IDLE – – B15 – SATA_PORT1_TXN MGT_X1Y1 TXNPAD6 A20 TARGET SATA_PORT1_TXP MGT_X1Y1 TXPPAD6 A19 – SATA_PORT1_RXN MGT_X1Y1 RXNPAD6 A17 – SATA_PORT1_RXP MGT_X1Y1 RXPPAD6 A18 – SATA_PORT1_IDLE – – AK3 – SATA_PORT2_TXN MGT_X2Y1 TXNPAD7 A14 HOST SATA_PORT2_TXP MGT_X2Y1 TXPPAD7 A13 – SATA_PORT2_RXN MGT_X2Y1 RXNPAD7 A11 – SATA_
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R Chapter 2: Using the System transmission using 0.5 meter and 1.0 meter SATA cables are shown in Figure 2-21.and Figure 2-22. Figure 2-21: 1.5 Gb/s Serial Data Transmission over 0.5 meter of SATA Cable Figure 2-22: 1.5 Gb/s Serial Data Transmission over 1.0 meter of SATA Cable 70 www.xilinx.com XUP Virtex-II Pro Development System UG069 (v1.
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R Appendix A Configuring the FPGA from the Embedded USB Configuration Port The XUP Virtex-II Pro Development System contains an embedded version of the Platform Cable USB for the purpose of configuration and programming the Virtex-II Pro FPGA and the Platform FLASH PROM using an off-the-shelf high-speed USB A-B cable. Configuration and programming are supported by iMPACT (v6.3.01i or later) download software using Boundary Scan (IEEE 1149.1/IEEE 1532) mode.
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R Appendix A: Configuring the FPGA from the Embedded USB Configuration Port Figure A-1: Device Manager Cable Entry There is no difference between the embedded Platform Cable USB implementation and the standalone Platform Cable USB hardware. The host computer operating system and iMPACT reports the attached cable as the standalone version.
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R When the Cable Communications Setup dialog box is displayed, the Communications Mode radio button must be set to Platform Cable USB as shown in Figure A-3. If no USB host is available, then select Parallel IV, attach a PC4 cable to J27. Figure A-3: iMPACT Cable Communication Setup Dialog Regardless of the native communications speed of the host USB port, target devices can be clocked at any of six different frequencies by making the appropriate selection in the TCK Speed/Baud Rate drop-down list.
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R Appendix A: Configuring the FPGA from the Embedded USB Configuration Port After the programming cable type and speed has been selected, the JTAG chain must be defined. Right click in the iMPACT window and select “Initialize Chain” from the dropdown menu shown in Figure A-4. Figure A-4: Initializing the JTAG Chain A status bar on the bottom edge of the iMPACT GUI provides useful information about the operating conditions of the software and the attached cable. If the host port is USB 1.
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R Figure A-5: Properly Identified JTAG Configuration Chain Right click on each of the devices in the chain and select “Assign New Configuration File” from the drop-down menu (see Figure A-6). The Platform FLASH PROM and the System ACE controller should be set to BYPASS, and the desired configuration file for the FPGA should be specified as shown in Figure A-7. Figure A-6: XUP Virtex-II Pro Development System UG069 (v1.0) March 8, 2005 Assigning Configuration Files to Devices in the JTAG Chain www.
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R Appendix A: Configuring the FPGA from the Embedded USB Configuration Port Figure A-7: Assigning a Configuration File to the FPGA Any additional files required by the design can specified at this time. Right click on the Virtex-II Pro FPGA and select “Program” to program the device as shown in Figure A-8. Figure A-8: 76 Programming the FPGA www.xilinx.com 1-800-255-7778 XUP Virtex-II Pro Development System UG069 (v1.
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R Appendix B Programming the Platform FLASH PROM User Area The XUP Virtex-II Pro Development System contains an XCF32P Platform FLASH PROM that is used to contain a known “Golden” configuration and a separate “User” configuration. These two FPGA configurations are supported by the design revisioning capabilities of the Platform FLASH PROMs. The “Golden” configuration is stored in Revision 0 and is write/erase protected, and the “User” configuration is stored in Revision 1.
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R Appendix B: Programming the Platform FLASH PROM User Area 2. Click on Next and select PROM File in the Prepare Configuration Files option menu shown in Figure B-2. Figure B-2: Selecting PROM File 3. Click on Next and then select Xilinx PROM with Design Revisioning Enabled using the MCS PROM File Format. 4. Give the PROM File a name of your choice in the location of your choice as shown in Figure B-3.
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R Figure B-3: Selecting a PROM with Design Revisioning Enabled 5. Click on Next to bring up the option screen where the type of PROM is specified. 6. Select the XCF32P PROM from the drop down men. Click on the “Add” button and specify “2” from the Number of Revisions drop down menu as shown in Figure B-4. Figure B-4: XUP Virtex-II Pro Development System UG069 (v1.0) March 8, 2005 Selecting an XCF32P PROM with Two Revisions www.xilinx.
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R Appendix B: Programming the Platform FLASH PROM User Area 7. Click on Next twice to bring up the Add Device File screen shown in Figure B-5. Figure B-5: 8. Click on Add File and navigate to your design directory and select the.bit file for your design as shown in Figure B-6. 9. Click on Open and answer No when prompted to add another design file to Revision 0. Figure B-6: 80 Adding a Device File Adding the Design File to Revision 0 www.xilinx.
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R 10. Note that Revision 0 is highlighted in green; this is where the “Golden” configuration will be placed in the PROM. By selecting your design file for Revision 0, you are just reserving space in the PROM for the “Golden” configuration. Your design file will not overwrite the “Golden” configuration because it is write/erase protected.
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R Appendix B: Programming the Platform FLASH PROM User Area Figure B-9: Generating the MCS File 13. When prompted to compress the file, respond No, because the XUP Virtex-II Pro Development System hardware does not support this option. 14. After iMPACT successfully creates the MCS file, select Configuration Mode from the Mode menu as shown in Figure B-10. Figure B-10: Switching to Configuration Mode 15.
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R Figure B-11: Initializing the JTAG Chain The iMPACT software then interrogates the system and reports that there are at least three devices in the JTAG chain. The first device is the XCF32P PROM; the second device is the System ACE controller; and the third device is the Virtex-II Pro FPGA. Any additional devices shown in the JTAG chain will reside on optional expansion boards. 17.
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R Appendix B: Programming the Platform FLASH PROM User Area 19. Right mouse click on the icon for the XCF32P PROM and select Program from the drop down menu as shown in Figure B-13. Figure B-13: Programming the PROM 20. The iMPACT software responds with a form that allows the user to specify which design revisions are to be programmed and the programming options for the various revisions. De-select Design Revision Rev 0 and all of the options for Design Revision Rev 0 to minimize the programming time.
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R Figure B-14: PROM Programming Options 23. Click on OK to begin programming the PROM. The iMPACT transcript window shows the sequence of operations that took place and looks similar to Figure B-15. Figure B-15: XUP Virtex-II Pro Development System UG069 (v1.0) March 8, 2005 iMPACT PROM Programming Transcript Window www.xilinx.
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R Appendix B: Programming the Platform FLASH PROM User Area 24. To load the newly programmed PROM configuration file into the Virtex-II Pro FPGA, verify that the “CONFIG SOURCE” switch is set to enable high-speed SelectMap bytewide configuration from the on-board Platform Flash configuration PROM, and that the “PROM VERSION” switch is set to enable the “User” configuration. If the switches are set properly, only the green “PROM” LED (D19) is illuminated. 25.
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R Appendix C Restoring the Golden FPGA Configuration The XUP Virtex-II Pro Development System contains an XCF32P Platform FLASH PROM that is used to contain a known Golden configuration and a separate User configuration. These two FPGA configurations are supported by the design revisioning capabilities of the Platform FLASH PROMs. The Golden configuration is stored in Revision 0 and is write/erase protected, and the User configuration is stored in Revision 1.
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R Appendix C: Restoring the Golden FPGA Configuration 3. Start up iMPACT and select Configure Devices as shown in Figure C-1. Figure C-1: 4. 88 System Operation Mode Selection: Configure Devices Clock on Next and select the Boundary Scan Mode from the option menu shown in Figure C-2. www.xilinx.com Xilinx University Program Virtex-II Pro Development 1-800-255-7778 UG069 (v1.
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R Figure C-2: Selecting Boundary Scan Mode Xilinx University Program Virtex-II Pro Development Systemwww.xilinx.com UG069 (v1.
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R Appendix C: Restoring the Golden FPGA Configuration 5. Figure C-3: 90 System Click on Next and then select Automatically connect to the cable and identify the Boundary Scan as shown in Figure C-3. Boundary Scan Mode Selection: Automatically Connect to the Cable and Identify the JTAG Chain 6. Click on Finish and the iMPACT software then interrogates the system and reports that there are at least three devices in the JTAG chain.
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R Figure C-4: Assigning New PROM Configuration File 8. Select BYPASS as the configuration files for the System ACE controller and the VirtexII Pro FPGA. 9. Right mouse click on the icon for the XCF32P PROM and select Erase from the drop down menu as shown in Figure C-5. When the erase options screen appears, select All Revisions and then click OK. Xilinx University Program Virtex-II Pro Development Systemwww.xilinx.com UG069 (v1.
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R Appendix C: Restoring the Golden FPGA Configuration Figure C-5: Erasing the Existing PROM Contents The iMPACT software then erases the complete contents of the PROM, including old versions of the Golden and User designs. The transcript window should look similar to Figure C-6. Figure C-6: Transcript Window for the Erase Command 10. Right mouse click on the icon for the XCF32P PROM and select Program from the drop down menu as shown in Figure C-7. 92 System www.xilinx.
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R Figure C-7: Selecting the Program Command 11. The iMPACT software responds with a form that allows the user to specify which design revisions are to be programmed and the programming options for the various revisions. Select Design Revision Rev 0 and set the Write Protect (WP) bit to prevent the user from overwriting the Golden configuration. Verify that the Operating Mode is set to Slave and the I/O Configuration is set to Parallel Mode as shown in Figure C-8.
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R Appendix C: Restoring the Golden FPGA Configuration Figure C-8: PROM Programming Options 12. Click on OK to begin programming the PROM. The iMPACT transcript window shows the sequence of operations that took place and looks similar to Figure C-9. 94 System www.xilinx.com Xilinx University Program Virtex-II Pro Development 1-800-255-7778 UG069 (v1.
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R Figure C-9: iMPACT PROM Programming Transcript Window 13. To load the newly programmed PROM configuration file into the Virtex-II Pro FPGA, verify that the CONFIG SOURCE switch is set to enable high speed SelectMap byte wide configuration from the on-board Platform Flash configuration PROM and that the PROM VERSION switch is set to enable the Golden configuration. If the switches are set properly, the green PROM CONFIG LED (D19) and the amber GOLDEN GONFIG LED (D14) are illuminated. 14.
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R 96 System Appendix C: Restoring the Golden FPGA Configuration www.xilinx.com Xilinx University Program Virtex-II Pro Development 1-800-255-7778 UG069 (v1.
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R Appendix D Using the Golden FPGA Configuration for System Self-Test Clock Generator VGA Char. & Test Pattern Generator PPC 1 External Port Test Audio Tones & Push Buttons Silicon Ser Number A special design has been placed in the Platform FLASH PROM to provide a Built-in SelfTest (BIST) boot/configuration that tests critical board features and reports on board health and status. Figure D-1 shows BIST block diagram.
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R Appendix D: Using the Golden FPGA Configuration for System Self-Test Compact Flash or download, but the “Golden Boot” has been designed to verify that the board is not damaged due to user abuse. This mode allows the user to verify that the board itself is not the root cause of a design failing to function properly. The BIST is a combination of pure hardware and processor centric tests combined into one FPGA design. The “Golden Boot” design covers the following elements of the system: 1.
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R Hardware-Based Tests 5. Connect the negative lead of the multimeter to J35 and the positive lead to J34. The meter should read between 1.425V and 1.575V, and LED D19 “1.5V OK” should be on. 6. Install the Shorting Jumper Block on JP2, LED D17 “2.5V OK” should be off, and D6 “RELOAD PS ERROR” should be on. Remove the Shorting Jumper Block. 7. Install the Shorting Jumper Block on JP6, LED D19 “1.5V OK” should be off, and D6 “RELOAD PS ERROR” should be on. Remove the Shorting Jumper Block. 8.
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R Appendix D: Using the Golden FPGA Configuration for System Self-Test 5. Briefly (less than 2 seconds), press the “RESET/RELOAD” push button SW1. This should result in the LEDs displaying the clock status again for 5 seconds. 6. Connect the headphones to the upper jack of J14 “AMP OUT.” Warning: Do not put the headphones on your ears, because the tones generated will be LOUD. 7. Press each one of the push buttons, SW2-6. A different tone will be produced as each push button is pressed.
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R Processor-Based Tests Silicon Serial Number and PS/2 Serial Port Test This test verifies the operation of the two PS/2 ports, as well as the one wire interface to the Silicon Serial Number. The board serial number is displayed on the SVGA display along with the key that was pressed on the PS/2 connected keyboard. A separate field on the SVGA display is used for each of the PS/2 ports.
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R Appendix D: Using the Golden FPGA Configuration for System Self-Test ug069 01a 021005 Figure D-2: Built-In Self-Test Main Menu Additional Hardware Required • 9-pin male-to-female straight-through serial communications (RS-232) cable • PC running Hyper Terminal or similar terminal program set to 9600 baud, 8-bit data, no parity, 1 stop bit, and no flow control. For a free PC terminal program, see: http://hp.vector.co.jp/authors/VA002416/teraterm.
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R Processor-Based Tests • PC running Hyper Terminal or similar terminal program.One 1.5 Gb/s rated serial ATA cable • One 1.5 Gb/s rated serial ATA cable This test begins when the “1” is selected from the Built-In Self-Test Main Menu displayed on the terminal window. The board should already have a serial ATA cable connected in a looped back configuration, between serial ATA 0 HOST and serial ATA 1 Target, or between serial ATA 2 HOST and serial ATA 1 Target. See Figure D-3 and Figure D-4.
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R Appendix D: Using the Golden FPGA Configuration for System Self-Test 6. The user is prompted to select which loop to test (Figure D-5). Figure D-5: 7. After entering “1” from the “Main Menu” in the terminal window, select which of the two serial ATA pairs you would like to run the test on. See Figure D-6. Figure D-6: 8.
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R Processor-Based Tests If there is a serious problem or the test was started without a cable connected to either loop path, you may see the message shown in Figure D-8 displayed on your terminal window. Figure D-8: No Link Established Error Message Once you type into the terminal window and the test starts, the user can change the default settings, for example, the internal serial loopback or the parallel loopback, and continue as shown in Figure D-9.
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R Appendix D: Using the Golden FPGA Configuration for System Self-Test . Figure D-10: SATA Loopback Test PASSED EMAC Web Server Test This test begins when “2” is selected from the BIST Main Menu. It verifies the operation of the EMAC controller, the functionality of the EMAC PHY, and the connection between the EMAC controller and the PHY by running a simple Web server on the PowerPC.
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R Processor-Based Tests Figure D-11: Specifying IP Address for XUP Virtex-II Pro Development System Note the following issues: a. For this test, the MAC address of the XUP board is set to: 00:11:22:33:44:55. If your LAN needs you to register your MAC address to enable access, please contact your LAN manager to register this MAC address. However, if you use a crossover cable, this issue does not apply. b. Input a valid IP address for your LAN environment.
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R Appendix D: Using the Golden FPGA Configuration for System Self-Test 2. Open a Web browser, and type in “http://YOUR XUP PRO BOARD IP ADDRESS:8080” in for the address, and you will see a Web page sent from the XUP Pro board as shown in Figure D-13. Figure D-13: 3. You can click the “Submit” button on the Web page without entering anything in the text box to reload the Web page. The background of the Web page will change each time it is reloaded. 4.
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R Processor-Based Tests AC97 Audio Test This test begins when “3” is selected from the BIST Main Menu. It verifies the operation of the AC97 CODEC for three different modes as selected by the user from the AC97 Audio. Test Menu shown in Figure D-15. Figure D-15: Selecting the Specific AC97 Audio Test 1. Digital Passthrough – the CODEC is configured to pass the data from the input channels (line-in, mic-in) directly to the output channels (line-out, amp-out). 2.
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R Appendix D: Using the Golden FPGA Configuration for System Self-Test Figure D-16: Digital Passthrough Test Completion FIFO Loopback Test Procedure 1. Select “2” from the AC97 Audio Test Menu. 2. Begin playing the audio from the PC (or other audio source). 3. The sound should be heard from the headphones (or speakers) for about 10 seconds. 4. The terminal window output for the FIFO Loopback test is shown in Figure D-17.
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R Processor-Based Tests Figure D-18: Game Sounds Test Completion At any time during the audio tests, when one of the push buttons is pressed, the corresponding beep is also played on the output jack. System ACE Test This test begins when “4" is selected from the BIST Main Menu. It checks the functionality of the SYSACE controller interface. System ACE Test Procedure 1. After you selected “4" in the BIST Main Menu, the program checks if there is a Compact Flash or Microdrive in the System ACE socket.
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R Appendix D: Using the Golden FPGA Configuration for System Self-Test DDR SDRAM Test This test begins when “5” is selected from the BIST Main Menu. It first uses the serial detect lines to determine if a DIMM module is seated in the memory slot. If one is identified, it proceeds to read the configuration registers to determine if the module is currently supported by the XUP Virtex-II Pro Development System.
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R Processor-Based Tests Figure D-20: 2. DDR SDRAM Test Completion In the case of an error, the following is an example of what would be printed: Running Data Walking 1’s Test…FAILED! Address: 0x00000000, Expected: 0x0000000000000001, Actual: 0x0000000100000001 Expansion Port Test This test verifies the connectivity of the FPGA to the four expansion headers, the two lowspeed expansion ports, and the single high-speed expansion port. The design creates a walking one pulse across the 80-bit expansion bus.
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R Appendix D: Using the Golden FPGA Configuration for System Self-Test ug076_21_021005 Figure D-21: Confirming Start of the Expansion Port Walking Ones Test 3. Connect the oscilloscope ground lead to any of the pins on the top row of J1-J4. These are all ground (GND) pins. If J1-J4 are not installed, then connect the oscilloscope ground lead to the GND pin of J36, the “DEBUG PORT.” This pin is clearly identified on the PCB silkscreen. 4.
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R Appendix E User Constraint Files (UCF) This appendix outlines the User Constraint Files (UCF) that are required to properly define the signal pinout of the Virtex-II Pro FPGA, as well as the input-output switching levels, drive strengths, and slew rates. The UCF file information is broken down by function and only the sections required for the user design need to be included in the UCF file for the actual design.
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R Appendix E: User Constraint Files (UCF) ## PINOUT AND IO DRIVE CHARACTERISTICS FOR THE CLOCKING ## SECTION OF THE XUP-V2PRO DEVELOPMENT SYSTEM ## REVISION C PRINTED CIRCUIT BOARD DEC 8 2004 ## DEFINE THE CLOCKS FOR THE MGTs NET "MGT_CLK_P" LOC = "F16"; NET "MGT_CLK_N" LOC = "G16"; NET "EXTERNAL_CLOCK_P" LOC = "G15"; NET "EXTERNAL_CLOCK_N" LOC = "F15"; NET NET NET NET "MGT_CLK_P" IOSTANDARD = LVDS_25; "MGT_CLK_N" IOSTANDARD = LVDS_25; "EXTERNAL_CLOCK_P" IOSTANDARD = LVDS_25; "EXTERNAL_CLOCK_N" IOSTANDAR
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R ## PINOUT AND IO DRIVE CHARACTERISTICS FOR THE CPU DEBUG ## SECTION OF THE XUP-V2PRO DEVELOPMENT SYSTEM ## REVISION C PRINTED CIRCUIT BOARD DEC 8 2004 NET NET NET NET NET NET NET "CPU_TDO" LOC = "AG16"; "CPU_TDI" LOC = "AF15"; "CPU_TMS" LOC = "AJ16"; "CPU_TCK" LOC = "AG15"; "CPU_TRST" LOC = "AC21"; "CPU_HALT_Z" LOC = "AJ23"; "PROC_RESET_Z" LOC = "AH5"; NET NET NET NET NET NET NET "CPU_TDO" IOSTANDARD = LVCMOS25; "CPU_TDI" IOSTANDARD = LVCMOS25; "CPU_TMS" IOSTANDARD = LVCMOS25; "CPU_TCK" IOSTANDARD = L
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R Appendix E: User Constraint Files (UCF) ## PINOUT AND IO DRIVE CHARACTERISTICS FOR THE USER LEDS ## OF THE XUP-V2PRO DEVELOPMENT SYSTEM ## REVISION C PRINTED CIRCUIT BOARD DEC 8 2004 118 NET NET NET NET "LED_0" "LED_1" "LED_2" "LED_3" LOC LOC LOC LOC = = = = "AC4"; "AC3"; "AA6"; "AA5"; NET NET NET NET "LED_0" "LED_1" "LED_2" "LED_3" IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD NET NET NET NET "LED_0" "LED_1" "LED_2" "LED_3" DRIVE DRIVE DRIVE DRIVE NET NET NET NET "LED_0" "LED_1" "LED_2" "LE
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R ## PINOUT AND IO DRIVE CHARACTERISTICS FOR THE 10/100 ETHERNET ## SECTION OF THE XUP-V2PRO DEVELOPMENT SYSTEM ## REVISION C PRINTED CIRCUIT BOARD DEC 8 2004 NET NET NET NET NET NET NET "TX_DATA[0]" LOC = "J7"; "TX_DATA[1]" LOC = "J8"; "TX_DATA[2]" LOC = "C1"; "TX_DATA[3]" LOC = "C2"; "TX_ERROR" LOC = "H2"; "TX_CLOCK" LOC = "D3"; "TX_ENABLE" LOC = "C4"; NET "TX_DATA[*]" IOSTANDARD = LVTTL; NET "TX_DATA[*]" DRIVE = 8; NET "TX_DATA[*]" SLEW = SLOW; NET "TX_ERROR" IOSTANDARD = LVTTL; NET "TX_ERROR" DRIVE =
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R Appendix E: User Constraint Files (UCF) NET NET NET NET NET NET "ENET_SLEW0" "ENET_SLEW1" "ENET_SLEW0" "ENET_SLEW1" "ENET_SLEW0" "ENET_SLEW1" NET NET NET NET NET NET "MDIO" "MDC" "MDIO" "MDC" "MDIO" "MDC" IOSTANDARD = LVTTL; IOSTANDARD = LVTTL; DRIVE = 8; DRIVE = 8; SLEW = SLOW; SLEW = SLOW; IOSTANDARD = LVTTL; IOSTANDARD = LVTTL; DRIVE = 8; DRIVE = 8; SLEW = SLOW; SLEW = SLOW; NET "MDINIT_Z" IOSTANDARD = LVTTL; NET "PAUSE" IOSTANDARD = LVTTL; NET "PAUSE" DRIVE = 8; NET "PAUSE" SLEW = SLOW; NET "S
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R ## PINOUT AND IO DRIVE CHARACTERISTICS FOR THE USER PUSH BUTTONS ## OF THE XUP-V2PRO DEVELOPMENT SYSTEM ## REVISION C PRINTED CIRCUIT BOARD DEC 8 2004 NET NET NET NET NET "PB_ENTER" LOC = "AG5"; "PB_UP" LOC = "AH4"; "PB_DOWN" LOC = "AG3"; "PB_LEFT" LOC = "AH1"; "PB_RIGHT" LOC = "AH2"; NET NET NET NET NET "PB_ENTER" IOSTANDARD = LVTTL; "PB_UP" IOSTANDARD = LVTTL; "PB_DOWN" IOSTANDARD = LVTTL; "PB_LEFT" IOSTANDARD = LVTTL; "PB_RIGHT" IOSTANDARD = LVTTL; XUP Virtex-II Pro Development System UG069 (v1.
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R Appendix E: User Constraint Files (UCF) ## PINOUT AND IO DRIVE CHARACTERISTICS FOR THE UPPER ## EXPANSION HEADER OF THE XUP-V2PRO DEVELOPMENT SYSTEM ## REVISION C PRINTED CIRCUIT BOARD DEC 8 2004 NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET "EXP_IO_0" LOC = "K2"; "EXP_IO_1" LOC = "L2"; "EXP_IO_2" LOC = "N8"; "EXP_IO_3" LOC = "N7"; "EXP_IO_4" LOC = "K4"; "EXP_IO_5" LOC = "K3"; "EXP_IO_6" LOC = "L1"; "EXP_IO_7" LOC = "M1"; "EXP_IO_8" LOC = "N6"; "EXP_IO_9" LOC = "N5"; "
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R ## PINOUT AND IO DRIVE CHARACTERISTICS FOR THE UPPER MIDDLE ## EXPANSION HEADER OF THE XUP-V2PRO DEVELOPMENT SYSTEM ## REVISION C PRINTED CIRCUIT BOARD DEC 8 2004 NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET "EXP_IO_20" "EXP_IO_21" "EXP_IO_22" "EXP_IO_23" "EXP_IO_24" "EXP_IO_25" "EXP_IO_26" "EXP_IO_27" "EXP_IO_28" "EXP_IO_29" "EXP_IO_30" "EXP_IO_31" "EXP_IO_32" "EXP_IO_33" "EXP_IO_34" "EXP_IO_35" "EXP_IO_36" "EXP_IO_37" "EXP_IO_38" "EXP_IO_39" LOC LOC LOC LOC LOC LOC
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R Appendix E: User Constraint Files (UCF) ## PINOUT AND IO DRIVE CHARACTERISTICS FOR THE LOWER MIDDLE ## EXPANSION HEADER OF THE XUP-V2PRO DEVELOPMENT SYSTEM ## REVISION C PRINTED CIRCUIT BOARD DEC 8 2004 NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET "EXP_IO_40" "EXP_IO_41" "EXP_IO_42" "EXP_IO_43" "EXP_IO_44" "EXP_IO_45" "EXP_IO_46" "EXP_IO_47" "EXP_IO_48" "EXP_IO_49" "EXP_IO_50" "EXP_IO_51" "EXP_IO_52" "EXP_IO_53" "EXP_IO_54" "EXP_IO_55" "EXP_IO_56" "EXP_IO_57" "EXP_IO_
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R ## PINOUT AND IO DRIVE CHARACTERISTICS FOR THE LOWER ## EXPANSION HEADER OF THE XUP-V2PRO DEVELOPMENT SYSTEM ## REVISION C PRINTED CIRCUIT BOARD DEC 8 2004 NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET "EXP_IO_60" "EXP_IO_61" "EXP_IO_62" "EXP_IO_63" "EXP_IO_64" "EXP_IO_65" "EXP_IO_66" "EXP_IO_67" "EXP_IO_68" "EXP_IO_69" "EXP_IO_70" "EXP_IO_71" "EXP_IO_72" "EXP_IO_73" "EXP_IO_74" "EXP_IO_75" "EXP_IO_76" "EXP_IO_77" "EXP_IO_78" "EXP_IO_79" LOC LOC LOC LOC LOC LOC LOC LOC
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R Appendix E: User Constraint Files (UCF) ## PINOUT AND IO DRIVE CHARACTERISTICS FOR THE LEFT LOW SPEED ## EXPANSION PORT OF THE XUP-V2PRO DEVELOPMENT SYSTEM ## REVISION C PRINTED CIRCUIT BOARD DEC 8 2004 NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET "EXP_IO_8" LOC = "N6"; "EXP_IO_9" LOC = "N5"; "EXP_IO_10" LOC = "L5"; "EXP_IO_11" LOC = "L4"; "EXP_IO_12" LOC = "M2"; "EXP_IO_13" LOC = "N2"; "EXP_IO_14" LO
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R ## PINOUT AND IO DRIVE CHARACTERISTICS FOR THE RIGHT LOW SPEED ## EXPANSION PORT OF THE XUP-V2PRO DEVELOPMENT SYSTEM ## REVISION C PRINTED CIRCUIT BOARD DEC 8 2004 NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET "EXP_IO_45" "EXP_IO_46" "EXP_IO_47" "EXP_IO_48" "EXP_IO_49" "EXP_IO_50" "EXP_IO_51" "EXP_IO_52" "EXP_IO_53" "EXP_IO_54" "EXP_IO_55" "EXP_IO_56" "EXP_IO_57" "EXP_IO_58" "EXP_IO_59" "EXP_IO_60" "EXP_IO_61" "EXP_IO_62"
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R Appendix E: User Constraint Files (UCF) ## PINOUT AND IO DRIVE CHARACTERISTICS FOR THE HIGH SPEED ## EXPANSION PORT OF THE XUP-V2PRO DEVELOPMENT SYSTEM ## REVISION C PRINTED CIRCUIT BOARD DEC 8 2004 128 NET NET NET NET "HS_IO[*]" IOSTANDARD = LVTTL; "HS_CLKOUT" IOSTANDARD = LVTTL; "HS_CLKIN" IOSTANDARD = LVCMOS25; "HS_CLKIO" IOSTANDARD = LVTTL; NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET N
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R ## PINOUT AND IO DRIVE CHARACTERISTICS FOR THE USER SWITCHES ## OF THE XUP-V2PRO DEVELOPMENT SYSTEM ## REVISION C PRINTED CIRCUIT BOARD DEC 8 2004 NET NET NET NET "SW_0" "SW_1" "SW_2" "SW_3" LOC LOC LOC LOC = = = = "AC11"; "AD11"; "AF8"; "AF9"; NET NET NET NET "SW_0" "SW_1" "SW_2" "SW_3" IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD = = = = LVCMOS25; LVCMOS25; LVCMOS25; LVCMOS25; ## PINOUT AND IO DRIVE CHARACTERISTICS FOR THE PS/2 ## PORTS OF THE XUP-V2PRO DEVELOPMENT SYSTEM ## REVISION C PRINTED
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R Appendix E: User Constraint Files (UCF) ## PINOUT AND IO DRIVE CHARACTERISTICS FOR THE DDR SDRAM ## SECTION OF THE XUP-V2PRO DEVELOPMENT SYSTEM ## REVISION C PRINTED CIRCUIT BOARD DEC 8 2004 130 NET NET NET NET NET NET NET NET NET NET NET NET NET "SDRAM_DQ[*]" "SDRAM_CB[*]" "SDRAM_DQS[*]" "SDRAM_DM[*]" "SDRAM_CK*" "SDRAM_CK*_Z" "SDRAM_A[*]" "SDRAM_BA*" "SDRAM_RAS_Z" "SDRAM_CAS_Z" "SDRAM_WE_Z" "SDRAM_S*_Z" "SDRAM_CKE*" IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTA
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R ############################################# # NET REQUIRED FOR XMIL IMPLEMENTATION ############################################# #NET "RST_DQS_DIV" LOC = "P27" ; #NET "RST_DQS_DIV" LOC = "P26" ; NET "SDRAM_DQS[7]" LOC = "AH26" ; NET "SDRAM_DM[7]" LOC = "W25" ; NET "SDRAM_DQ[63]" LOC = "AH29" ; NET "SDRAM_DQ[62]" LOC = "AH27" ; NET "SDRAM_DQ[61]" LOC = "AG28" ; NET "SDRAM_DQ[60]" LOC = "AD25" ; NET "SDRAM_DQ[59]" LOC = "AD26" ; NET "SDRAM_DQ[58]" LOC = "AG29" ; NET "SDRAM_DQ[57]" LOC = "AG30" ; NET "SDR
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R Appendix E: User Constraint Files (UCF) NET NET NET NET NET NET NET NET NET NET "SDRAM_DQS[3]" "SDRAM_DM[3]" "SDRAM_DQ[31]" "SDRAM_DQ[30]" "SDRAM_DQ[29]" "SDRAM_DQ[28]" "SDRAM_DQ[27]" "SDRAM_DQ[26]" "SDRAM_DQ[25]" "SDRAM_DQ[24]" LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC = = = = = = = = = = "P29" "T22" "N28" "N27" "P24" "P23" "P30" "M28" "M27" "R22" ; ; ; ; ; ; ; ; ; ; NET NET NET NET NET NET NET NET NET NET "SDRAM_DQS[2]" "SDRAM_DM[2]" "SDRAM_DQ[23]" "SDRAM_DQ[22]" "SDRAM_DQ[21]" "SDRAM_DQ[20]" "SD
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R ## PINOUT AND IO DRIVE CHARACTERISTICS FOR THE SYSTEMACE ## MPU PORT OF THE XUP-V2PRO DEVELOPMENT SYSTEM ## REVISION C PRINTED CIRCUIT BOARD DEC 8 2004 NET NET NET NET NET NET NET "CF_MPA[0]" "CF_MPA[1]" "CF_MPA[2]" "CF_MPA[3]" "CF_MPA[4]" "CF_MPA[5]" "CF_MPA[6]" LOC LOC LOC LOC LOC LOC LOC = = = = = = = "AF21"; "AG21"; "AC19"; "AD19"; "AE22"; "AE21"; "AH22"; NET "CF_MPA[*]" IOSTANDARD = LVCMOS25; NET "CF_MPA[*]" DRIVE = 8; NET "CF_MPA[*]" SLEW = SLOW; NET NET NET NET NET NET NET NET NET NET NET NET
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R Appendix E: User Constraint Files (UCF) ## PINOUT AND IO DRIVE CHARACTERISTICS FOR THE XSGA ## VIDEO OUTPUT OF THE XUP-V2PRO DEVELOPMENT SYSTEM ## REVISION C PRINTED CIRCUIT BOARD DEC 8 2004 NET NET NET NET NET "VGA_VSYNCH" LOC = "D11"; "VGA_HSYNCH" LOC = "B8"; "VGA_OUT_BLANK_Z" LOC = "A8"; "VGA_COMP_SYNCH" LOC = "G12"; "VGA_OUT_PIXEL_CLOCK" LOC = "H12"; NET NET NET NET NET NET NET NET "VGA_OUT_RED[7]" "VGA_OUT_RED[6]" "VGA_OUT_RED[5]" "VGA_OUT_RED[4]" "VGA_OUT_RED[3]" "VGA_OUT_RED[2]" "VGA_OUT_RED[1
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R NET NET NET NET NET "VGA_VSYNCH" SLEW = SLOW; "VGA_OUT_PIXEL_CLOCK" SLEW = SLOW; "VGA_HSYNCH" SLEW = SLOW; "VGA_OUT_BLANK_Z" SLEW = SLOW; "VGA_COMP_SYNCH" SLEW = SLOW; XUP Virtex-II Pro Development System UG069 (v1.0) March 8, 2005 www.xilinx.
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R Appendix E: User Constraint Files (UCF) ############################################################### # SATA 0 Host ############################################################### # MGT TX/RX pads are not directly specified in the UCF file. # Rather, the MGT itself is placed and the tools automatically # connect the appropriate pads. INST "hierarchical_path_to_mgt" LOC=GT_X0Y1; # SATA 0 HOST # In addition, constrain location of the registers in the MGT Phase # Align Module.
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R Appendix F Links to the Component Data Sheets This appendix provides links to the manufacturers’ web sites for the various components used in this system. FPGA Related Documentation • Virtex-II Pro Complete Data Sheet http://direct.xilinx.com/bvdocs/datasheets/ds083.pdf • Virtex-II Pro Platform FPGA User Guide http://direct.xilinx.com/bvdocs/userguides/ug012.pdf • RocketIO Transceiver User Guide http://direct.xilinx.com/bvdocs/userguides/ug024.
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R Appendix F: Links to the Component Data Sheets Audio Processing • AC 97 Multi-Channel Audio Codec http://cache.national.com/ds/LM/LM4550.pdf • 150 mW Stereo Audio Power Amplifier http://focus.ti.com/lit/ds/symlink/tpa6111a2.pdf XSGA Video Output • 180 MHz Triple Video D/A Converter http://www.fairchildsemi.com/ds/FM/FMS3818.pdf Ethernet Networking • Dual - Speed Single – Port Fast Ethernet Transceiver http://www.intel.com/design/network/products/lan/datashts/24918603.