User Manual

15
# Aux I/O 8 bit 2 x 4 connector JB
NET "AUX_JB<1>" LOC="L25";
NET "AUX_JB<2>" LOC="H33";
NET "AUX_JB<3>" LOC="J34";
NET "AUX_JB<4>" LOC="E31";
NET "AUX_JB<7>" LOC="F30";
NET "AUX_JB<8>" LOC="H34";
NET "AUX_JB<9>" LOC="K33";
NET "AUX_JB<10>" LOC="F31";
NET "AUX_JB<*>" IOSTANDARD = LVCMOS25;
# Aux I/O 4 bit 1 x 4 connector JC
NET "AUX_JC<1>" LOC="C34";
NET "AUX_JC<2>" LOC="D34";
NET "AUX_JC<3>" LOC="L26";
NET "AUX_JC<4>" LOC="G30";
NET "AUX_JC<*>" IOSTANDARD = LVCMOS25;
# SMA connector
NET “DIFSIG_1_p” LOC = “D1”;
NET “DIFSIG_1_n” LOC = “D2”;
NET “DIFSIG_2_p” LOC = “G3”;
NET “DIFSIG_2_n” LOC = “G4”;
When plugged into J64:
#
# User Constraint File for FMC-CE card when attached to a Xilinx ML605 – J64
# pin locations only!
#
# 2/26/2010
#
#
# Device
# Virtex6 xc6vlx240t fgg1156 SPEED_GRADE = -1
#
# *** peripherals ***
#
# LCD
NET "LCD_data_pins<0>" LOC = "AL24"; # gpio_lcd_db8
NET "LCD_data_pins<1>" LOC = "AN25";
NET "LCD_data_pins<2>" LOC = "AN24";
NET "LCD_data_pins<3>" LOC = "AP27";
NET "LCD_data_pins<4>" LOC = "AP26";