User Manual

PMCU Interface Connection

TEMPERATURE A Zynq Die Temperature

PORT_A, VADJ_A Zmod A

PORT_B, VADJ_B Zmod B

FAN_1 FPGA Fan

FAN_2 Case Fan

Table 1.6.2: Supported Platform MCU Optional Features

Optional Features Supported

DDRVCCSEL Control No

INIT_B Control No

USB Hub Support No

Table 1.6.3: Supported Platform MCU Fan COntrol Features

Feature FAN_1 (FPGA Fan) FAN_2 (Case Fan)

Enable / Disable Yes No

Fixed Speed Control Yes No

Automatic Speed Control Yes No

RPM Measurement Yes (if supported by installed fan) Yes (if supported by installed fan)

The optional FPGA fan included with the Eclypse Z7 supports RPM measurement

The case fan included in the Eclypse Z7 Enclosure Kit does not support RPM measurement

Unlike Xilinx FPGA devices, AP SoC devices such as the Zynq-7020 are designed around the processor, which acts as a master to the

programmable logic fabric and all other on-chip peripherals in the processing system. This causes the Zynq boot process to be more

similar to that of a microcontroller than an FPGA. This process involves the processor loading and executing a Zynq Boot Image, which

includes a First Stage Bootloader (FSBL), a bitstream for configuring the programmable logic (optional), and a user application.

The boot process is broken into three stages:

After the Eclypse Z7 is powered on or the Zynq is reset (in software or by pressing the PS-SRST button, BTNR), one of the processors

(CPU0) begins executing an internal piece of read-only code called the BootROM. If and only if the Zynq was just powered on, the

BootROM will first latch the state of the mode pins into the mode register (the mode pins are attached to JP5 on the Eclypse Z7). If the

BootROM is being executed due to a reset event, then the mode pins are not latched, and the previous state of the mode register is used.

This means that the Eclypse Z7 needs a power cycle to register any change in the programming mode jumper (JP5). Next, the BootROM

copies an FSBL from the form of non-volatile memory specified by the mode register to the 256 KB of internal

RAM (Random Access

Memory) within the APU (called On-Chip Memory, or OCM). The FSBL must be wrapped up in a Zynq Boot Image in order for the

BootROM to properly copy it. The last thing the BootROM does is hand off execution to the FSBL in OCM.

During this stage, the FSBL first finishes configuring the PS components, such as the DDR memory controller. Then, if a bitstream is

present in the Zynq Boot Image, it is read and used to configure the PL. Finally, the user application is loaded into memory from the

Zynq Boot Image, and execution is handed off to it.

1) 2)

2. Zynq Configuration

Stage 0

Sta

ge 1