User Manual

MIO 500 3.3
V
Peripherals
Pin
GPIO (General Purpose
Input/Output)
SPI Flash ENET 0 SYZYGY UART 0
0 (N/C)
1
CS (Chip Select (Active
High))
2 DQ0
3 DQ1
4 DQ2
5 DQ3
6
SCLK (SPI Clock)
7 (N/A)
8
SCLK (SPI Clock) FB
9 Ethernet
Reset
10 (N/A)
11 (N/A)
12 DNA SCL (I2C
0)
13 DNA SDA (I2C
0)
14 UART Input
15 UART
Output
MIO 16-53 : Bank 501
The PS consists of many components, including the Application Processing Unit (APU, which includes 2 Cortex-A9 processors),
Advanced Microcontroller Bus Architecture (AMBA) Interconnect, DDR3 Memory controller, and various peripheral controllers with
their inputs and outputs multiplexed to 54 dedicated pins (called Multiplexed I/O, or MIO pins). Peripheral controllers that do not have
their inputs and outputs connected to MIO pins can instead route their I/O through the PL, via the Extended-MIO (EMIO) interface.
The peripheral controllers are connected to the processors as slaves via the AMBA interconnect, and contain readable/writable control
registers that are addressable in the processors’ memory space. The programmable logic is also connected to the interconnect as a slave,
and designs can implement multiple cores in the FPGA fabric that each also contain addressable control registers. Furthermore, cores
implemented in the PL can trigger interrupts to the processors and perform DMA accesses to DDR3 memory.
There are many aspects of the Zynq APSoC architecture that are beyond the scope of this document. For a complete and thorough
description, refer to the

Zynq Te
chnical Reference manual (http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-
TRM.pdf).
The tables in the dropdowns below depict the external components connected to the MIO pins of the Eclypse Z7. The Vivado board
files found on the can be used to properly configure the PS to work with these peripherals. It is also possible to use the example
projects found on the resource center as a starting point for custom designs.
MIO 0-15 : Bank 500