User Manual

Signal Name Description Zynq Pin SD Slot Pin
SD_D3 Data[3] MIO45 2
SD_CCLK Clock MIO40 5
SD_CMD Command MIO41 3
SD_CD Card Detect MIO47 9
The SD slot is powered from 3.3V, but is connected through MIO Bank 1/501 (1.8V). Therefore, a TI TXS02612 level shifter performs
this translation. The TXS02612 is actually a 2-port SDIO port expander, but only its level shifter function is used. The connection
diagram can be seen on Figure 9.1. Mapping out the correct pins and configuring the interface is handled by the Eclypse Z7 board files,
available on the Eclypse Z7 Resource Center
Both low speed and high speed cards are supported, the maximum clock frequency being 50 MHz (Megahertz (million times per
second)). A Class 4 card or better is recommended.
Refer to section 2.1 microSD Boot Mode for information on how to boot from a microSD card that contains a Zynq Boot Image.
The microSD is also commonly used to store non-configuration data needed by the application. If doing this from a bare-metal
application, the microSD card can be freely accessed using standalone libraries included with a Xilinx SDK BSP project. If doing this
from a Petalinux generated embedded Linux system, the microSD can be mounted/accessed like a standard block device, typically with a
device node named /dev/mmcblk0. See the Petalinux and Xilinx SDK documentation for more information.
The Eclypse Z7 implements one of the two available PS USB OTG interfaces on the Zynq device. A Microchip USB3320 USB 2.0
Transceiver Chip with an 8-bit ULPI interface is used as the PHY. The PHY features a complete HS-USB Physical Front-End supporting
speeds of up to 480Mbs. The PHY is connected to MIO Bank 1/501, which is powered at 1.8V. The usb0 peripheral is used on the PS,
connected through MIO[28-39]. The USB OTG interface can act as an host, embedded host, or a peripheral device, through the USB
Micro AB connector(J5). The USB mode is controlled from software by manipulating the USB0 peripheral controller in the Zynq PS.
By default, VBUS capacitance is 4.7 µF. Jumper JP1 may be shorted while in host mode in order to increase VBUS capacitance by 150 µF.
Jumper JP2 must be installed for the Eclypse to power VBUS for host or embedded host applications. These requirements give three
possible configurations for the two jumpers, as presented in Table 10.1.
Whether the Eclypse Z7 is configured as an embedded host or a general purpose host, it can provide at least 500 mA on the 5V VBUS
line. More than 500 mA of current can potentially be provided depending on the system configuration and how much power is drawn by
installed Zmods. See the
1 Power Supplies section for more information.
Table 10.1: USB Mode Jumper Positions
Mode JP1 Shorted JP2 Shorted
Embedded Host No Yes
General Purpose Host Yes Yes
Peripheral Device No No
The Eclypse Z7 uses a Realtek RTL8211E-VL PHY to implement a 10/100/1000 Ethernet port for network connection. The PHY
connects to MIO Bank 501 (1.8V) and interfaces to the Zynq-7000 AP SoC via RGMII for data and MDIO for management. The
auxiliary interrupt (INTB) and reset (PHYRSTB) signals connect to PS pins to be accessed through the MIO
GPIO (General Purpose
Input/Output) peripheral via MIO48 and MIO9 respectively. The connection diagram can be seen on Figure 11.1.
10. USB Micro-AB Device/Host/OTG Port
11. Ether
net