User Manual
Parameter Port A (STD) Port B (STD)
Port Type Standard Standard
Double-Width Capable
Total 5V Supply Current 3.0 A (shared with USB VBUS output, Case Fan, and RGB LEDs)
Total 3.3V Supply Current 2.0 A Shared
VIO Supply Voltage Range 1.2V to 3.3V 1.2V to 3.3V
Total VIO Supply Current 1.8A (VIO Group 1) 1.8A (VIO Group 2)
Port Groups Group 1: A Group 2: B
I/O Count 28 total (8 DP) 28 total (8 DP)
Length Matching 73.7 mm +- 0.2 mm (including Zynq package delay)
The Eclypse Z7 provides a microSD slot (J4) for non-volatile external memory storage as well as booting the Zynq. The slot is wired to
Bank 1/501 MIO[40-45], and also includes a card detect signal attached to MIO 47. On the PS side, peripheral SDIO 0 is mapped out to
these pins and controls communication with the SD card. The pinout can be seen in Table 9.1. The peripheral controller supports 1-bit
and 4-bit SD transfer modes, but does not support SPI mode. Based on the
Zynq Technical Reference Manual
(http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf), SDIO host mode is the only mode supported.
Table 9.1: microSD pinout
Signal Name Description Zynq Pin SD Slot Pin
SD_D0 Data[0] MIO42 7
SD_D1 Data[1] MIO43 8
SD_D2 Data[2] MIO44 1
The Eclypse Z7 features two Zmod ports, which use SYZYGY Standard interfaces to communicate with installed SYZYGY pods. Both
ports are compatible with version 1.1 of the SYZYGY specification from Opal Kelly.
SYZYGY SmartVIO functionality is implemented by the Eclypse's Platform MCU, as discussed in the 1 Power Supplies section of this
document. Each port's SYZYGY DNA is connected to both the Platform MCU and the Zynq's I2C 0 peripheral (MIO12:13) through a
single I2C bus. Once the board is fully powered on, and the PMCU has configured itself in I2C slave mode, SYZYGY DNA data can be
read directly from the pods, and the negotiated voltages and currents can be read from the PMCU over this bus.
Warning: SYZYGY pods are NOT hot-swappable. Connecting or disconnecting a pod from the Eclypse while the board is powered on may cause damage to
the pod and/or the board, and is to be avoided.
Each SYZYGY Standard interface contains 16 single-ended I/O pins, 8 differential I/O pairs (which can alternatively be used as 16
additional single-ended I/O pins), and two dedicated differential clocks - one for input and one for output. Each Zmod port has a I/O
bank of the Zynq dedicated to it, which is powered by a dedicated adjustable rail, configured by the Platform MCU as the Eclypse is
powered on. Template constraints for each Zmod port can be found in the Eclypse Z7's Master XDC file, available through Digilent's
digilent-xdc (https://github.com/Digilent/digilent-xdc) repository on Github.
Digilent provides Eclypse-compatible low-level IPs, scripted Vivado flows, and software libraries to support each Digilent Zmod.
For more information on the SYZYGY standard, see
syzygyfpga.io (https://syzygyfpga.io/).
8.1. SYZYGY Pod Compatibility
The Eclypse's Zmod ports are compatible with a variety of different SYZYGY pods. Information required to determine if the Eclypse is
compatible with a certain pod is summarized in Table 8.1.1.
Table 8.1.1: SYZYGY Compatibility Table
9. microSD Slot