User Manual

The Eclypse Z7 features a Spansion S25FL128S 4-bit Quad-SPI serial NOR flash. The key device attributes are:
Part number S25FL128S
16
MB (Megabyte) of memory
1-bit, 2-bit, and 4-bit bus widths supported
General use clock speeds up to 100
MHz (Megahertz (million times per second)), translating to 400 Mbps in Quad-SPI mode
Zynq configuration clock speeds up to 94
MHz (Megahertz (million times per second))
Powered from 3.3V
The Flash memory is used to provide non-volatile code and data storage. It can be used to initialize the PS and PL of the Zynq device
with a Zynq Boot Image (also known as BOOT.BIN) generated using Xilinx tools such as Petalinux or Xilinx SDK. For information on
booting the Eclypse Z7 with a Zynq Boot image, see section “2.2 Quad SPI Boot Mode”.
The Flash is also commonly used to store non-configuration data needed by the application. If doing this from a bare-metal application,
The flash memory can be freely accessed using standalone libraries included with a Xilinx SDK BSP project. If doing this from a
Petalinux generated embedded Linux system, the Flash can be partitioned as desired and mounted/accessed like a standard MTD block
device. See the Petalinux and Xilinx SDK documentation for more information.
The Flash connects to the Quad-SPI Flash controller of the Zynq-7000 PS via pins in MIO Bank 0/500 (specifically MIO[1:6,8]), as
outlined in the Zynq Technical Reference Manual. Quad-SPI feedback mode is used, thus qspi_sclk_fb_out/MIO[8] is left to freely
toggle and is connected only to a 20K pull-up resistor to 3.3V. This allows a Quad-SPI clock frequency greater than FQSPICLK2. The
details of these connections do not need to be known when using the Eclypse Z7 Vivado Board files, as they will automatically configure
your project to work correctly with the on-board Flash.
A globally unique MAC address is programmed into the One-Time-Programmable (OTP) region of the Flash on each Eclypse Z7 at the
factory. For more information on this, see section
11. Ethernet. The MAC address can also be found on a sticker attached to the board.
The OTP region also includes a factory-programmed read-only 128-bit random number. The very lowest address range [0x00;0x0F] can
be read to access the random number. See the Spansion S25FL128S datasheet for information on this random number and accessing the
OTP region.
ohm resistor on the ZQ pin.
Both the memory chips and the PS DDR bank are powered from the 1.35V supply. The mid-point reference of 0.675V is created with a
simple resistor divider and is available to the Zynq as external reference.
For proper operation it is essential that the PS memory controller is configured properly. Settings range from the actual memory flavor to
the board trace delays. For your convenience, the Eclypse Z7 Vivado board files are available on the Eclypse Z7 Resource Center
and automatically configure the Zynq Processing System IP core with the correct parameters.
For best DDR3L performance, DRAM training is enabled for write leveling, read gate, and read data eye options in the PS Configuration
Tool in Xilinx tools. Training is done dynamically by the controller to account for board delays, process variations and thermal drift.
Optimum starting values for the training process are the board delays (propagation delays) for certain memory signals.
Board delays are specified for each of the byte groups. These parameters are board-specific and were calculated from the PCB trace
length reports. The DQS to CLK Delay and Board Delay values are calculated specific to the Eclypse Z7 memory interface PCB design.
For more details on memory controller operation, refer to the Xilinx

Zynq Technical Reference manual
(http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf).
4. Quad-SPI Flash
5. Oscillators/Clocks
T
he Eclypse Z7 provides a 33.3333 MHz (Megahertz (million times per second)) clock to the Zynq PS_CLK input, which is used to
generate the clocks for each of the PS subsystems. The 33.3333 MHz (Megahertz (million times per second)) input allows the processor
to operate at a maximum frequency of 667 MHz (Megahertz (million times per second)) and the DDR3 memory controller to operate at
a maximum clock rate of 533 MHz (Megahertz (million times per second)) (1066 MT/s). The Eclypse Z7 board files, available on the
Eclypse Z7 Resource Center , will automatically configure the Zynq processing system IP core in Vivado to work with all PS attached
devices, including the 33.3333 MHz (Megahertz (million times per second)) input oscillator.
The PS has a dedicated PLL capable of generating up to four reference clocks, each with settable frequencies, that can be used to clock
custom logic implemented in the PL. Additionally, The Eclypse Z7 provides an external 125 MHz (Megahertz (million times per second))
reference clock directly to pin D18 of the PL. The external reference clock allows the PL to be used completely independently of the PS,
which can be useful for simple applications that do not require the processor.
The PL of the Zynq-Z7020 also includes four MMCM’s and four PLL’s that can be used to generate clocks with precise frequencies and
phase relationships. Any of the four PS reference clocks or the 125 MHz (Megahertz (million times per second)) external reference clock
can be used as an input to the MMCMs and PLLs. For a full description of the capabilities of the Zynq PL clocking resources, refer to