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ManualsBrandsDigilent ManualsDevelopment Boards & KitsEclypse Z7 Bundle with 2x Zmod ADC Analogue-to-Digital Converter Modules

The Eclypse Z7 is a powerful prototyping platform, featuring Xilinx's Zynq-7000 APSoC. Two SYZYGY interface connectors are

featured, enabling high speed modular systems.

Eclypse is designed to enable high speed analog data capture and analysis right out of the box. It is a platform for research and rapid

prototyping of test and measurement applications, potentially including software defined radio, ultrasound, other medical devices, and

much more. As a host board for Zmods applications for the Eclypse can vary significantly between system configurations.

Petalinux is supported out

of the box. Pre-built Linux images are accompanied by a software API (Application Programming Interface)

for bulk data transfer. This system allows new users to get started without touching hardware until desired. The software supports a

variety of common programming languages, including Python, C/C++, and more. Digilent offers fully open and customizable hardware

designs, Linux images, and Linux software applications.

Zynq-7000 APSoC (XC7Z020-1CLG484C)

667 MHz

(Megahertz (million times per second)) dual-core Cortex-A9 processor

DDR3L memory controller with 8 DMA channels and 4 High Performance AXI3 Slave ports

High-bandwidth peripheral controllers: 1G Ethernet, USB 2.0, SDIO

Low-bandwidth peripheral controllers: SPI, UART, CAN, I2C

Programmable from JTAG, Quad-SPI flash, and microSD card

Programmable logic equivalent to Artix-7 FPGA

Memory

1 GiB DDR3L with 32-bit bus @ 1066 MT/s

MB (Megabyte) Quad-SPI Flash with factory programmed 128-bit random number and 48-bit globally unique EUI-

48/64™ compatible identifier

microSD card slot

Power

Powered from external 12V 5A supply

Platform MCU for configuration of adjustable power supplies and temperature management

USB and Ethernet

Gigabit Ethernet PHY

USB-JTAG programming circuitry

USB-UART bridge

USB micro AB port with USB 2.0 PHY with Host/Device/OTG capabilities

Zmod Ports

2 ports following the SYZYGY Standard interface specification

Compatible with a variety of SYZYGY pods, allowing for a wide variety of applications

Dedicated differential clocks for input and output

8 differential I/Os per port

16 single-ended I/Os per port

DNA interfaces connected to Platform MCU allowing for various auto-negotiated power supply configurations

Pmod Ports

2 twelve-pin ports for a total of 16 FPGA-connected I/Os

High speed voltage translation and protection circuitry

User GPIO (General Purpose Input/Output)

2 push-buttons

2 RGB LEDs

Eclypse Z7 Callout Diagram

Callout

# Description

Callout

# Description

Callout

# Description

1 Board Indicator LEDs

(LD4)

7 SYZYGY Ports 13 Reset Buttons (underside of

board)

Eclypse Z7 Hardware Reference Manual

Features

Summary of content (15 pages)

PAGE 1
Eclypse Z7 Hardware Reference Manual The Eclypse Z7 is a powerful prototyping platform, featuring Xilinx's Zynq-7000 APSoC. Two SYZYGY interface connectors are featured, enabling high speed modular systems. Eclypse is designed to enable high speed analog data capture and analysis right out of the box. It is a platform for research and rapid prototyping of test and measurement applications, potentially including software defined radio, ultrasound, other medical devices, and much more.
PAGE 2
Callout # Description Callout # Description Callout # Description 2 Header for Case Power Switch 8 Pmod Ports 14 microSD Card Slot 3 Power Switch 9 User Buttons and LEDs 15 USB JTAG/UART Port 4 FPGA Fan Header 10 DDR3L Memory 16 Ethernet Port 5 Zynq-7000 SoC and FPGA Fan 11 Case Fan Header 17 USB AB Host/Device/OTG Port 6 External JTAG Port 12 Programming Mode Select Jumper 18 Power Supply Connector Purchasing Options The Eclypse Z7 includes an FPGA fan to dissipate extra
PAGE 3
The PS consists of many components, including the Application Processing Unit (APU, which includes 2 Cortex-A9 processors), Advanced Microcontroller Bus Architecture (AMBA) Interconnect, DDR3 Memory controller, and various peripheral controllers with their inputs and outputs multiplexed to 54 dedicated pins (called Multiplexed I/O, or MIO pins).
PAGE 4
MIO 501 1.
PAGE 5
45 D3 46 USB Reset 47 48 CD Ethernet Interrupt (GPIO (General Purpose Input/Output)) USB Overcurrent (GPIO (General Purpose Input/Output)) 49 50 (N/C) 51 (N/C) 52 MDC 53 MDIO Functional Description 1. Power Supplies The Eclypse Z7 power circuitry was carefully designed to meet the requirements of the Zynq-7000 and all peripherals while providing the flexibility needed to power a variety of different configurations of Zmod/SYZYGY modules.
PAGE 6
Net Name Upstream Net Name Power IC Type Power IC Label Min/Typ/Max Voltage Max. Current VCC5V0 VIN12V0 Buck IC27 5.0V +-5% 3A Zmods, USB OTG VBUS, RGB LEDs, Case Fan VCC1V0 VIN12V0 Buck IC27 1.0V +-5% 1A Zynq, Ethernet, USB OTG, USB JTAG/UART, microSD DDR1V35 VIN12V0 Buck IC25 1.35V +-5% 2A Zynq, DDR3L DDRVTT VIN12V0 LDO IC21 0.675V +-5% 0.45A DDR3L VCC3V3 VIN12V0 Buck IC25 3.3V +-5% 3.
PAGE 7
Port Rail Max Capacitance (µF) Zmod Port A VIO 1000 Zmod Port B VCC5V0 500 Zmod Port B VCC3V3 500 Zmod Port B VIO 1000 Pmod Port A VCC3V3 500 Pmod Port B VCC3V3 500 1.3. Power Sequencing A custom power sequencer (IC29) is used to sequence the power supplies on in the correct order when the power switch is placed in the “ON” position. The power supplies shut down in the opposite order when the power switch is moved to the “OFF” position. The startup sequence is as follows: 1. 2. 3. 4. 5.
PAGE 8
PMCU Interface Connection TEMPERATURE A Zynq Die Temperature PORT_A, VADJ_A Zmod A PORT_B, VADJ_B Zmod B FAN_1 FPGA Fan FAN_2 Case Fan Table 1.6.2: Supported Platform MCU Optional Features Optional Features Supported DDRVCCSEL Control No INIT_B Control No USB Hub Support No Table 1.6.
PAGE 9
Stage 2 The last stage is the execution of the user application that was loaded by the FSBL. This can be any sort of program, from a simple baremetal “Hello World” application, to a Second Stage Boot loader used to boot an operating system like Linux. For a more thorough explanation of the boot process, refer to Chapter 6 of the  Zynq Technical Reference Manual (http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf).
PAGE 10
ohm resistor on the ZQ pin. Both the memory chips and the PS DDR bank are powered from the 1.35V supply. The mid-point reference of 0.675V is created with a simple resistor divider and is available to the Zynq as external reference. For proper operation it is essential that the PS memory controller is configured properly. Settings range from the actual memory flavor to the board trace delays.
PAGE 11
the 7 Series FPGAs Clocking Resources User Guide (https://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf) available from Xilinx. Xilinx offers the Clocking Wizard IP core to assist in integrating the MMCM's and PLL's into a design. This wizard will properly instantiate the needed MMCMs and PLLs based on the desired frequencies and phase relationships specified by the user.
PAGE 12
The Eclypse Z7 features two Zmod ports, which use SYZYGY Standard interfaces to communicate with installed SYZYGY pods. Both ports are compatible with version 1.1 of the SYZYGY specification from Opal Kelly. SYZYGY SmartVIO functionality is implemented by the Eclypse's Platform MCU, as discussed in the 1 Power Supplies section of this document. Each port's SYZYGY DNA is connected to both the Platform MCU and the Zynq's I2C 0 peripheral (MIO12:13) through a single I2C bus.
PAGE 13
Signal Name Description Zynq Pin SD Slot Pin SD_D3 Data[3] MIO45 2 SD_CCLK Clock MIO40 5 SD_CMD Command MIO41 3 SD_CD Card Detect MIO47 9 The SD slot is powered from 3.3V, but is connected through MIO Bank 1/501 (1.8V). Therefore, a TI TXS02612 level shifter performs this translation. The TXS02612 is actually a 2-port SDIO port expander, but only its level shifter function is used. The connection diagram can be seen on Figure 9.1.
PAGE 14
21/02/2020 Eclypse Z7 Hardware Reference Manual [Reference.Digilentinc] After power-up the PHY starts with Auto Negotiation enabled, advertising 10/100/1000 link speeds and full duplex. If there is an Ethernet-capable partner connected, the PHY automatically establishes a link with it, even with the Zynq not configured. Two status indicator LEDs are located on the RJ-45 connector (J3) that indicate traffic (J3/LD2, right side of connector) and valid link state (J3/LD1, left side of connector). Table 11.
PAGE 15
LED (Light Emitting Diode), the corresponding PL pins need to be driven high. The tri-color LED (Light Emitting Diode) will emit a color dependent on the combination of internal LEDs that are currently being illuminated. For example, if the red and blue signals are driven high and green is driven low, the tri-color LED (Light Emitting Diode) will emit a purple color. Note: Digilent strongly recommends the use of pulse-width modulation (PWM) when driving the tri-colo LEDs.