User manual

Zybo Z7 Board Reference Manual
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Page 20 of 31
Figure 10.1. Ethernet PHY signals.
Two status indicator LEDs are on-board near the RJ-45 connector that indicate traffic (LD8) and valid link state
(LD7). Table 10.1 shows the default behavior.
Function
Designator
State
Description
LINK
LD7
Steady on
Link 10/100/1000
Blinking 0.4s ON, 2s OFF
Link, Energy Efficient Ethernet (EEE)
mode
ACT
LD8
Blinking
Transmitting or Receiving
Table 10.1. Ethernet status LEDs.
The Zynq incorporates two independent Gigabit Ethernet Controllers. They implement a 10/100/1000 half/full
duplex Ethernet MAC. Of these two, GEM 0 can be mapped to the MIO pins where the PHY interfaces. Since the
MIO bank is powered from 1.8V, the RGMII interface uses 1.8V HSTL Class 1 drivers. For this I/O standard an
external reference of 0.9V is provided in bank 501 (PS_MIO_VREF). Mapping out the correct pins and configuring
the interface is handled by the Zybo Z7 Vivado board files.
Although the default power-up configuration of the PHY might be enough in most applications, the MDIO bus is
available for management. The RTL8211E-VL is assigned the 5-bit address 00001 on the MDIO bus. With simple
register read and write commands, status information can be read out or configuration changed. The Realtek PHY
follows industry-standard register map for basic configuration.
The RGMII specification calls for the receive (RXC) and transmit clock (TXC) to be delayed relative to the data
signals (RXD[0:3], RXCTL and TXD[0:3], TXCTL). Xilinx PCB guidelines also require this delay to be added. The
RTL8211E-VL is capable of inserting a 2ns delay on both the TXC and RXC so that board traces do not need to be
made longer.