Datasheet

Zybo Z7 Board Reference Manual

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Page 16 of 30

Xilinx offers the Clocking Wizard IP core to assist in integrating the MMCM's and PLL's into a design. This wizard

will properly instantiate the needed MMCMs and PLLs based on the desired frequencies and phase relationships

specified by the user. The wizard will then output an easy-to-use wrapper component around these clocking

resources that can be inserted into the user’s design. The clocking wizard can be accessed from within the Vivado

and IP Integrator tools.

Figure 5.1 outlines the clocking scheme used on the Zybo Z7. Note that the reference clock output from the

Ethernet PHY is used as the 125 MHz reference clock to the PL, in order to cut the cost of including a dedicated

oscillator for this purpose. Keep in mind that CLK125 will be disabled when the Ethernet PHY is held in hardware

reset by driving the PHYRSTB signal low.

Figure 5.1. Zybo Z7 clocking.

6 Reset Sources

The Zybo Z7 provides several different methods of resetting the Zynq-7000 device, as described in the following

sections.

6.1 Power-on Reset

The Zynq PS supports external power-on reset signals. The power-on reset is the master reset of the entire chip.

This signal resets every register in the device capable of being reset. The Zybo Z7 drives this signal from the

PWRGD signal of the ADP5052 power regulator in order to hold the system in reset until all power supplies are

valid.

6.2 Programmable Logic Reset

A red push button, labeled PROGB, toggles the Zynq-7000's PROG_B input. This resets the PL and causes DONE to

be de-asserted. The PL will remain unconfigured until it is reprogrammed by the processor or via JTAG.

6.3 Processor Subsystem Reset

The external system reset button, labeled PS-SRST, resets the Zynq device without disturbing the debug

environment. For example, the previous break points set by the user remain valid after system reset. Due to

security concerns, system reset erases all memory content within the PS, including the On-Chip-Memory (OCM).