User Manual

61 USB20_DATA5
62 USB20_DATA6
63 USB20_DATA7
64 USB20H_CLK
65 USB20H_DIR
66 USB20H_DATA2
67 USB20H_NXT
68 USB20H_DATA0
69 USB20H_DATA1
70 USB20H_STP
71 USB20H_DATA3
72 USB20H_DATA4
73 USB20H_DATA5
74 USB20H_DATA6
75 USB20H_DATA7
76 ETH_MDC
77 ETH_MDIO
The Genesys ZU power distribution network was designed to meet the specific requirements of Xilinx Zynq UltraScale+ MPSoCs and of
the supported peripheral devices. Power to the board is provided via a 2×3 PCIe ATX power connector. Xilinx evaluation boards use a
pinout that is not compatible with ATX, therefore mixing power supplies is not possible. The bundled supply is 12V 60W-100W,
depending on variant. The board power supplies are turned on or off with the SW5 slide switch.
Figure 1.2.1: Genesys ZU power distribution network and supply sequencing
Note: The VCC0V9_MGTAVCC* and VCC0V9_VCU* rails are not used on the Genesys ZU-3EG variant.
Functional Description
1. Power Supplies
1.1. Power Input
1.2. Power Specifications
Figure 1.2.1 gives an overview of the Genesys ZU power distribution network.
Figure 1.2.1. Genesys ZU power distribution network and supply sequencing