User Manual

Feature/Peripheral IP support Version
SFP+*
PL soft-core, 10G/25G Ethernet Subsystem, license required
2019.1
HDMI 2.0
Source/Sink*
PL soft-core, HDMI Subsystem, license required
2019.1
Video PHY
Controller*
PL soft-core, WebPACK built-in, requires protocol-implementation like the HDMI Subsystem
above, supported by 5EV only
2019.1
The initial Vivado version supported by Digilent for Genesys ZU-related projects is 2019.1. Digilent currently does not provide hardware
platforms or examples for Xilinx's Vitis Unified Software Platform, however Vitis support is planned for the near future.
Design resources, example projects, and tutorials are available for download at the Genesys ZU Resource Center
MIO
500 3.3
V
Peripherals
Pin QSPI Mini PCIe /
SATA
DDR4
SODIMM
MIO
Buttons
WI-FI UART MIO
LED
()
0 QSPI_SCLK0OUT
1 QSPI_D1
2 QSPI_D2
3 QSPI_D3
4 QSPI_D0
5 QSPI_SS_OUTN
6(N/C)


Zynq UltraScale+ MPSoC Architecture
Zynq UltraScale+ MPSoC is the Xilinx second-generation Zynq platform, combining a powerful processing system (PS) and user-
programmable logic (PL) into the same device. The Zynq UltraScale+ Processing System core acts as a logic connection between the PS
and the Programmable Logic (PL) while assisting you to integrate customized and integrated IP cores with the processing system using
the Vivado IP integrator. As you may see in the picture below, the processing system features the Arm flagship Cortex -A53 64-bit quad-
core running up to 1.5GHz and Cortex-R5 dual-core real-time processor along with other interfaces such as: DDR Memory Controller,
High-Connectivity, General Connectivity, System Functions etc. The Zynq UltraScale+ MPSoC Processing System wrapper instantiates
the processing system section of the Zynq UltraScale+ MPSoC for the programmable logic and external board logic. The wrapper
Figure II: Zynq UltraScale+ EG
The PS and PL can be coupled with multiple interfaces and other signals to effectively integrate user-created hardware accelerators and
other functions in the PL logic that are accessible to the processors. The interfaces between the processing system and programmable
logic mainly consist of three main groups: the extended multiplexed I/O (EMIO), programmable logic I/O, and the AXI I/O groups.
Besides those, there are up to 78 Multiplexed I/O (MIO) ports available from the processing system. The 78 MIO signals are divided
into three banks, and each bank includes 26 device pins. Each bank (500, 501, and 502) has its own power pins for the hardware
interface.
MIO 0-25 : Bank 500