User Manual

Attachment detection is implemented by the Platform MCU and pod presence is communicated to the MPSoC over the
SYZYGY_DETECTED signal. For now, it is up to the MPSoC to read the port's SYZYGY DNA and implement SmartVIO
functionality by requesting a compatible voltage on the VADJ rail. SYZYGY DNA is accessible on branch 5 of the I C multiplexer on
the main I C bus at address 0110000b.
SYZYGY pods are NOT hot-swappable. Connecting or disconnecting a pod from the Genesys ZU while the board is
powered on may cause damage to the pod and/or the board, and is to be avoided.
Each SYZYGY Standard interface contains 14 single-ended I/O pins (2 of which I C), 8 differential I/O pairs (which can alternatively
be used as 16 additional single-ended I/O pins), and two dedicated differential clocks - one for input and one for output. The Zmod port
is wired to PL-side MPSoC banks powered by the VADJ rail, sharing them with FMC signals. Therefore if both an FMC mezzanine card
and a Zmod are connected to the Genesys ZU, a common voltage supported by both needs to be chosen for VADJ. The differential pairs
were prioritized and wired to HP banks, allowing the maximum data rates supported by the SelectI/O architecture. However, the single-
ended pins are wired to an HD bank, limiting the data rate to 250 Mb/s according to the Zynq UltraScale+ MPSoC Data Sheet: DC and
AC Switching Characteristics
(ds925) (https://www.xilinx.com/support/documentation/data_sheets/ds925-zynq-ultrascale-plus.pdf). Template
constraints for the Zmod port can be found in the Genesys ZU's Master XDC file, available through Digilent's digilent-xdc
(https://github.com/Digilent/digilent-xdc) repository on Github.
For more information on the SYZYGY standard, see
syzygyfpga.io (https://syzygyfpga.io/).
The Genesys ZU Zmod port is compatible with a variety of different SYZYGY pods. Information required to determine if the Genesys
ZU is compatible with a certain pod is summarized in Table 8.3.1.1.
Table 8.3.1.1: SYZYGY Compatibility
Parameter Port A (STD)
Port Type Standard
Single-Width
Total 5V Supply Current 1 A
Total 3.3V Supply Current 3.5 A (shared with FMC)
VIO Supply Voltage Range 1.2V to 1.8V
Total VIO Supply Current 2.1 A (shared with FMC)
Port Groups Group 1: A
I/O Count 28 total (8 DP)
Length Matching 10 mm inter-pair, 1mm intra-pair
Is there any information on this not encapsulated by the syzygy spec ()?
Add S-parameter reports
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8.3.1. SYZYGY Pod Compatibility
8.3.2
8.4. Pmod
Pmod ports are 2×6, right-angle, 100-mil spaced female connectors that mate with standard 2×6 pin headers. Each 12-pin Pmod port
provides two 3.3V VCC () signals (pins 6 and 12), two Ground signals (pins 5 and 11), and eight logic signals