User Manual

J13 socket implements a versatile expansion option for adding
SSD (), WLAN, Bluetooth or WWAN modules to the Genesys ZU. It is
compatible with PCI Express Mini card types F1/F2 (Full-Mini) and H1/H2 (Half-Mini) and mSATA card types Mini and Full size.
Mechanical compatibility is assured by the relocatable stand-offs included with the board. Electrically, the SATA lane and the PCIe x1
lane share the same PS-GTR transceiver lane. Therefore, it is up to the MPSoC configuration to enable either the SATA or the PCIe
Root controller and map it to the GTR lane. Mini PCIe modules can also make use of the embedded USB 2.0 port wired to the on-board
USB hub and the MPSoC USB1 controller up the chain.
Quad Primitive Pin type Pin FMC signal
224 GTHE4_CHANNEL X0Y7 MGTHTXP/N3 N4/N3 DP0_C2M_P/N
MGTHRXP/N3 P2/P1 DP0_M2C_P/N
Signal Group Length matching
Intra-pair Inter-pair
LA[00-33], CLK[0-1]_M2C 1 mm 10 mm
DP0*, GBTCLK0* 0.14 mm 100 mm
Add impedance, net length, length matching and S-parameter reports
The Zmod port uses the SYZYGY Standard interface to communicate with installed SYZYGY pods. The port is compatible with
version 1.1 of the SYZYGY specification from Opal Kelly.
8.2. Low-Pin Count FMC Connector
The Genesys ZU includes an FPGA Mezzanine Card (FMC) Standard-conforming carrier card connector that enables connecting
mezzanine modules compliant with the same standard. Genesys ZU-based designs can now be easily extended with custom or off-the-
shelf high-performance modules.
The actual connector used is a 160-pin Samtec ASP-134603-01, the low-pin count, 10mm stacking height variant of the standard. All user
defined signals are bonded to the PL-side of the MPSoC to HP banks 64 and 65. On the 5EV variant the multi-gigabit transceiver lane is
also wired to the PL-side GTH transceiver, sharing the lane with the SFP+ slot.* The 34 differential pairs are powered by the Genesys
ZU VADJ rail adjustable in the 1.2 V - 1.8 V range.
FMC mezzanine cards are NOT hot-swappable. Connecting or disconnecting a card from the Genesys ZU while the board
is powered on may cause damage to the mezzanine card and/or the board, and is to be avoided.
The UltraScale+ HP banks support the highest data rates available in the non-GT I/O architecture over the FMC connector.
The pin-out of the FMC connector can be found in the XDC constraints file available on reference.digilentinc.com. The schematic also
shows the mapping between FMC connector pins and FPGA pins. Keep in mind that pin designators for the connector are not the same
as pin designators for the FPGA specified in the XDC constraints file. For example, the connector pin with designator H28 and named
LA24_P is wired via net FMC_LA24_P to the FPGA pin with designator AF7 and named IO_L11P_T1U_N8_GC_64. In the
constraints file FMC_LA24_P will need to be location constrained to AF7.
For above-gigabit speed rates on the 5EV variant, the gigabit transceiver lane is wired to a multiplexer. The SFP+ slot and the FMC share
a single GTH lane through the multiplexer. Therefore, only one of them can be used at any time. The FMC user defined pins are not
affected by this limitation. Each transceiver lane includes a receive pair and a transmit pair. Lane DP0 is wired through the mux to quad
224. The reference clock GBTCLK0 goes to a jitter filter and can be sent to MGTREFCLK0 pins of the same quad. Table 8.2.1 shows
how the FMC gigabit signals are mapped to pins and GTH primitives.
For FMC designs which use FMC_LA_07_P/_N and/or FMC_LA15_P/_N lines with an I/O standard which needs DCI, please make
sure you add the DCIRESET primitive to the respective designs.
Table 8.2.2: Maximum length mismatch including MPSoC package delay.
8.3. Zmod