User Manual

The micro Type-B connector J8 connects to an FTDI FT4232HQ USB bridge. It provides a JTAG interface for programming and

debugging, one UART interface connected to the MPSoC and one UART interface connected to the Platform MCU. The UART

interfaces are exposed as standard COM ports. Their exact designator is determined upon enumeration, but the first one will always

connect to the MPSoC and the second one to the Platform MCU. The MPSoC UART interface is wired to the PS-side MIO Bank 500:

UART_TXD_IN to MIO18 and UART_RXD_OUT to MIO19. Signal names that imply direction are from the point-of-view of the

DTE (Data Terminal Equipment), in this case the PC (e.g. UART_TXD_IN is the TXD signal of the DTE, meaning it is an output of

the DTE and an input of the DCE). The Digilent USB-JTAG function and the USB-UART functions behave independent of one

another. Support for USB-JTAG in Vivado is expected in version 2020.1.

The dual-lane mini DisplayPort connector J27 is wired to a PS-side DisplayPort Controller via two PS-GTR transceiver lanes. Resolutions

up to 4Kx2K@30fps are supported at a maximum 5.4Gbps line rate.

TODO for 5EV

The Genesys ZU board includes an Analog Devices ADAU1761 SigmaDSP audio codec (IC39) complementing its multimedia features.

Four 1/8” (3.5mm) audio jacks are available for line-out (J20-green), headphone-out (J19-black), line-in (J22-blue), and microphone-in

(J21-pink). Each jack carries two channels of analog audio (stereo), with the exception of the microphone input, which is mono.

To record or play back audio the audio data needs to be converted. The audio codec bridges the gap between the analog jacks and the

digital FPGA pins. It connects to the PL side of the MPSoC. Analog-to-digital and digital-to-analog conversion is done at up to 24 bits

and 96

kHz () sampling rate. Digital audio data is carried to/from the FPGA on a serial, full-duplex interface, which supports several

different formats, the default being I2S. This interface is clocked by the FPGA through BCLK by default, but the codec can be

configured to provide the clock itself.

Configuring the audio codec can be done over I C. It responds to slave address 0b0111011 on a dedicated I C bus, followed by a 16-bit

The codec is clocked from the FPGA through the Master Clock (MCLK) pin. A clock must be provided for the codec to function,

including the I C port. The exact frequency depends on the desired sample rate and whether PLL will be used, but 12

MHz () is a good

start.

For proper use, the concept of audio paths needs to be understood. Internal to the codec there are two signal paths: Playback and

Record. Both are highly configurable analog paths with mixers and amplifiers that route audio signals through the chip. The Playback

path is the output path that routes audio from different sources like the digital-to-analog converter or input mixers towards the

headphone and line out jacks. On the other hand, the record path routes audio from the line-in and microphone-in towards the analog-

to-digital converters. Having routing elements at every step enables signal mixing between channels, amplification, muting and bypass.

However, it also means that each element has to be properly configured along the path.

Keep in mind that audio jack designations might differ from codec analog frontend designators. For example, the line-in jack connects to

the AUX port of the codec. The microphone jack is wired to the IN port. Also, notice that although some ports offer differential

amplifiers and signaling, they are not used on the Genesys ZU. For example, the OUT port is differential, comprising 4 pins: LOUTP,

LOUTN, ROUTP, and ROUTN. However, the N-side of the differential pairs is left floating, while the P-side connects to the jack.

At the very least an audio-aware FPGA design should do the following:

1. Provide MCLK for the audio codec.

2. Use an I C master controller to configure the core clocking, sample rates, serial interface format and audio path.

3. Send or receive audio samples over the serial audio data channel for playback or record.

More advanced users might want to try additional features of the ADAU1761. For example, the on-chip SigmaDSP core can be

programmed to do user-defined digital signal processing.

7. Multimedia

7.1. DisplayPort Source

7.2. HDMI Source

7.3. HDMI Sink

7.4. Audio Codec

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