User Manual
Although the default power-up configuration of the PHY might be enough in most applications, the MDIO bus is available for
management. The PHY is assigned the 5-bit address 01111 on the MDIO bus. With simple register read and write commands, status
information can be read out or configuration changed. The TI PHY follows industry-standard register map for basic configuration.
The RGMII specification calls for the receive (RXC) and transmit clock (TXC) to be delayed relative to the data signals (RXD[0:3],
RXCTL and TXD[0:3], TXCTL). Xilinx PCB guidelines also require this delay to be added. The PHY is configured to insert a delay of
2.0ns between RXD/CTL and RXC, and a delay of 1.5ns between TXD/CTL and TXC.
On an Ethernet network each node needs a unique MAC address. To this end, the last sector of the Quad-SPI flash has been
programmed at the factory with a 48-bit globally unique EUI-48/64™ compatible identifier. For more details about MAC address
storage see
Quad-SPI Flash.
Boot has been
patched (https://github.com/Digilent/Genesys-ZU-OOB-os/commit/7eac6c368efd33042e95eb78abac5c16d87020c4) to read
this MAC address and overwrite the existing node in the device tree binary before handing control over to the Linux kernel.
The identifier is also printed on a sticker found next to the Ethernet jack (J14).
Todo for 5EV.
The Mini PCIe socket allows you to connect any wireless radio module compatible with the PCIe Mini Card standard. With both PCIe x1
and USB 2.0 available in the socket, even dual Wi-Fi/Bluetooth modules can be used. The primary use case is Linux
OS (), so modules
with Linux drivers available in-kernel are recommended. For WWAN radio modules a SIM slot is present on the bottom side of the
board.
USB 3.1 Gen1 and USB 2.0 support is handled by the Full-Featured Type-C receptacle J6. The connector has a USB 2.0 pair for
backward compatibility, one high-speed transceiver lane (two pairs) for USB 3.1, and configuration channel (CC). Since the plug is
reversible, the upper and lower rows double the number of pins for each function, designated by suffixes 1 and 2. Plug orientation is
established during the configuration process over the CC1 and CC2 pins. Depending on the orientation, either pins with suffix 1 or pins
with suffix 2 carry actual signals. Multiplexing 1 and 2 for the USB 3.1 lane is done by an on-board hardware multiplexer.
Unlike the other USB connector types, Type-C does not inherently establish the relationship of host and device ports. This relationship is
determined during the same configuration process.
On the Genesys ZU, data behavior is Dual-Role-Data (DRD), ie. can behave either as a Downstream-Facing Port (DFP) or an Upstream-
Facing Port (UFP), depending on the connected partner and MPSoC configuration. Power behavior is Dual-Role-Power (DRP), but even
if UFP is negotiated, the board remains self-powered. In DFP role the advertised current capability and limit is 0.9 A with the possibility
of increasing it to 1.5 A. USB Power Delivery is not supported.
Management of the Type-C port is handled by a companion chip, the TI TUSB322I. It handles attachment, cable orientation, role
detection and current advertisment. It connects to the main I C bus of the board and can be used to read status and set port roles for
Type-C. It responds to address 1000111b on branch 3 of the I C multiplexer.
The USB 2.0 pair is implemented by a Microchip USB3320 PHY interfacing with the PS-side controller of MPSoC over ULPI. The USB
3.1 lane is implemented using a PS-GTR transceiver lane.
In the box you can find a USB Type-C Legacy Adapter reference as CAR3G1-3 in the Type-C specifications. It has a Full-Featured Type-
C plug on one end and a USB 3.1 Standard-A receptacle on the other. Use it to connect non-Type-C USB 2.0 or USB 3.1 devices to the
Genesys ZU.
Host-only USB 2.0 functionality is implemented by a Microchip USB3320 PHY and a Microchip USB2513B hub. The PHY is wired to
the PS-side controller of MPSoC over ULPI. The hub has three Downstream-Facing Ports. Two of these connect to a dual-stacked Type-
A connector, providing 0.5A current per port. The third port is connected to the MiniPCIe slot, an embedded USB port. This allows
interfacing with Bluetooth modules, for example.
5.3. 10G SFP+
5.4. WLAN, Bluetooth, WWAN
6. Peripheral Connectivity
6.1. USB Full-Featured Type-C
2
2
6.2. USB 2.0 Host
6.3. USB 2.0 - JTAG/Serial Bridge