User Manual

The Flash is also commonly used to store non-configuration data needed by the application. If doing this from a bare-metal application,
the flash memory can be freely accessed using standalone libraries included with a Xilinx SDK BSP project. If doing this from a
Petalinux generated embedded Linux system, the Flash can be partitioned as desired and mounted/accessed like a standard MTD block
device. See the Petalinux and Xilinx SDK documentation for more information.
The Flash connects to the Quad-SPI Flash controller of the Zynq UltraScale+ via pins in MIO Bank 0/500 (specifically MIO[0:5]).
The memory is divided into uniform 4 KByte sectors or uniform 32/64 Kbyte blocks. A block consists of 8/16 adjacent sectors.
Two globally unique MAC address are programmed in the last sector, sector 8191.
MAC for Ethernet PHY is stored at address 0x1FFF000
MAC for SFP+ (5EV only) is stored at address 0x1FFF006
The microSD connector J9 located on the top side has a hinge-based mechanism. It is compatible with UHS-I allowing 1.8V signalling
and speeds up to SDR104, or 104MB/s. To enable UHS-I support and speeds up to SDR104, see the following Answer Records from
Xilinx:
https://www.xilinx.com/support/answers/69978.html (https://www.xilinx.com/support/answers/69978.html) and
https://www.xilinx.com/support/answers/70062.html (https://www.xilinx.com/support/answers/70062.html).
The Mini PCIe connector J13 doubles as an mSATA slot allowing fast non-volatile
SSD () storage. Both half and full-size modules are
supported. Since PCIe and SATA share the same GTR lanes, one has to disable PCIe first to enable SATA.
A Microchip ATWINC1500 module provides 2.4GHz IEEE 802.11 b/g/n wireless network connectivity. It interfaces to the MPSoC on
the PS-side over SPI, supporting a maximum theoretical data rate of 48Mbps. The ATWINC1500 can be used in bare-metal applications
with the full IP stack included in the firmware loaded from flash. However, it is also supported in Linux in the ATWILC1000-compatible
mode, where the firmware is loaded on-the-fly upon boot and the
OS () IP stack is used.
The Genesys ZU uses a TI DP83867CR PHY to implement a 10/100/1000 Ethernet port for wired connectivity. The PHY connects to
MIO Bank 501 (1.8V) and interfaces to the MPSoC via RGMII for data and MDIO for management. The auxiliary interrupt
(ETH_INTN_PWDNN) and reset (ETH_RSTN) signals also connect to MIO Bank 501.
After power-up the PHY starts with Auto Negotiation enabled, advertising 10/100/1000 link speeds and full duplex. If there is an
Ethernet-capable partner connected, the PHY automatically establishes a link with it, even with the MPSoC not configured.
Three status indicator LEDs are on-board near the RJ-45 connector that indicate speed (LD13), valid link state (LD12), and traffic
activity (LD14).
The last sector, used to store the MAC addresses, is protected from write and erase. Any attempt to program or erase the last sector will
fail.
The ISSI flash features an Advanced Sector/Block Protection mechanism. Every main flash memory array block/top sector/bottom
sector has a non-volatile (PPB) protection bit associated with it. When the bit is 0, the sector is protected from program and erase
operations.
There is a TBPARM bit that defines the logical location of the parameter block. The parameter block consists of thirty two 4KB sectors,
which replace two 64KB blocks.
When TBPARM is set to 0 the parameter block is in the top of the memory array address space. When TBPARM is set to 1 the
parameter block is at the bottom of the array. TBPARM is OTP(One-Time Programmable) and set to 1 when shipped from factory. If
TBPARM is programmed to 0, an attempt to change it back to 1 will fail and ignore the program operation.
To protect the MAC addresses from the last sector, Genesys ZU comes with TBPARM programmed to 0 and the PPB bits for the last
sector programmed to 0.
4.2. microSD slot
 
4.3. mSATA slot
5. Network Connectivity
5.1. Wi-Fi
5.2. 1G Ethernet