User Manual

ManualsBrandsDigilent ManualsDigilentDigilent Genesys ZU: Zynq Ultrascale+ MPSoC Development Board

The black matte board you are holding in your hand is a prototyping and evaluation board

proudly designed by Digilent. At its heart is a Xilinx Zynq UltraScale+ MPSoC ARM-FPGA

hybrid, coupled with upgradeable memory, network and multimedia interfaces, and a wide

variety of expansion connectors making it a versatile computing platform.

Available in two variants, 3EG and 5EV, differentiated by the MPSoC model and some

peripherals. If the fan sticker says 5EV, on top of 3EG you get slightly faster DDR4, more

FPGA, video codec and GTH transceivers allowing HDMI Source, Sink and SFP+ 10G.

Used stand-alone with a hearty bundle in the box, powered by the 12V power supply, it straight

up boots Linux from the microSD card. Connect the USB micro B cable to a PC and open a

terminal (115200-8-N-1) to the first COM port out of the two that appear. Login and password

are both “root”. The red button labeled “POR” always resets the MPSoC and starts the boot

process again.

Want to dive deep into development? Head over to our

GitHub page

(https://github.com/Digilent) and use the repos there as a starting point. Build your own boot

image on the SD card and boot it like the OOB demo. Not enough? Connecting the JTAG-

HS1/HS2 cable to header J28 will allow for on-the-fly programming and debug using Xilinx

Vivado and SDK.

The Digilent Genesys ZU is a stand-alone Zynq UltraScale+ MPSoC prototyping and development board. It is an advanced computing

platform with powerful multimedia and network connectivity interfaces. The excellent mix of on-board peripherals, upgrade-friendly

DDR4, Mini PCIe and microSD slots, multi-camera and high-speed expansion connectors are bound to support a wide number of use-

cases. Furthermore, the Genesys ZU is available in two variants with different MPSoC options and additional features for even more

flexibility. Differences are highlighted* throughout this document.

The Xilinx Zynq UltraScale+ MPSoC at the heart of the Genesys ZU is a big leap from the Zynq-7000 series. Faster and more processor

cores, upgraded memory interface, integrated gigabit transceivers bring support for DDR4, USB Type-C 3.1, PCIe, SATA, DisplayPort,

SFP+* and HDMI*. The Genesys ZU is primarily targeted towards Linux-based applications that allows easy access to Wi-Fi, cellular

radio (WWAN),

SSD (), USB SuperSpeed and 4K video. The bundled microSD card includes an out-of-box demo that boots a Linux

image built in Petalinux and includes some test scripts for some of the peripherals.

Genesys ZU Reference Manual

TL;DR



Summary of content (24 pages)

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Genesys ZU Reference Manual TL;DR The black matte board you are holding in your hand is a prototyping and evaluation board proudly designed by Digilent. At its heart is a Xilinx Zynq UltraScale+ MPSoC ARM-FPGA hybrid, coupled with upgradeable memory, network and multimedia interfaces, and a wide variety of expansion connectors making it a versatile computing platform. Available in two variants, 3EG and 5EV, differentiated by the MPSoC model and some peripherals.
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Features Feature group Sub-feature Processor APU Quad A53 Dual A9 RPU Dual R5 ✘ Main Memory Genesys ZU -3EG DDR4, 4GB, 1866 MT/s, upgradeable Programmable logic # of logic cells Peripheral connectivity USB Type-C 3.
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Feature group Sub-feature Genesys ZU -3EG Genesys ZU -5EV USB 2.0 Host Network connectivity 2 x Type-A 1 x OTG 2.4GHz ✘ ✔ ✘ (w/o IEEE 1588) option - MiniPCIe ✘ On-board Wi-Fi Ethernet 1G w/ IEEE 1588 WLAN / WWAN / LoRa ✘ SFP+ 10G Ethernet Storage Multimedia Expansion ✔ ✘ 104 MB ()/s 25 MB ()/s SSD () option - mSATA ✘ Flash ISSI 256 Mib SNOR 128 Mib DisplayPort 1.
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Callout # Description Callout # Description 7 Audio jacks 19 User buttons 8 Boot mode select jumper 20 MIPI (Pcam) connectors 9 Reset buttons 21 Wireless and SSD () activity LEDs 10 INIT, DONE, ERR and STS Leds 22 MicroSD Card Slot 11 Zmod (SYZYGY) connector 23 Mini DisplayPort 12 FMC LPC connector 24 1G Ethernet port Callout # Description Software Support Zynq UltraScale+ MPSoC platforms are well-suited to be embedded Linux targets, and the Genesys ZU is no exception.
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Feature/Peripheral IP support Version SFP+* PL soft-core,  10G/25G Ethernet Subsystem, license required 2019.1 HDMI 2.0 Source/Sink* PL soft-core,  HDMI Subsystem, license required 2019.1 Video PHY Controller* PL soft-core, WebPACK built-in, requires protocol-implementation like the HDMI Subsystem above, supported by 5EV only 2019.1 The initial Vivado version supported by Digilent for Genesys ZU-related projects is 2019.1.
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PCIE_PERSTN 8 DDR_SCL 9 DDR_SDA 10 BTN1 11 BTN0 12 WIFI_PORTEX_SCK 13 14 15 WIFI_SSN 16 WIFI_PORTEX_MISO () 17 WIFI_PORTEX_MOSI () 18 UART_TXD_IN 19 UART_RXD_OUT 20 PCIE_WAKEN 21 LD0 22 23 24 25 Note: The WI-FI signals are shared by the same bus that goes through the I/O expander. MIO 26-51 : Bank 501 MIO 501 1.
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33 ETH_RX_D0 34 ETH_RX_D1 35 ETH_RX_D2 36 ETH_RX_D3 37 ETH_RX_CTL 38 ETH_INTN_PWDNN 39 SDIO_SEL 40 SDIO_DIR_CMD 41 SDIO_DIR_DAT0 42 SDIO_DIR_DAT1_3 43 SDIO_POW_EN 44 ETH_RSTN 45 SDIO_CDN 46 SDIO_R_DAT0 47 SDIO_R_DAT1 48 SDIO_R_DAT2 49 SDIO_R_DAT3 50 SDIO_R_CMD 51 SDIO_R_SCLK () MIO 52-77 : Bank 502 MIO 502 1.8V Peripherals Pin USB 2.
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61 USB20_DATA5 62 USB20_DATA6 63 USB20_DATA7 64 USB20H_CLK 65 USB20H_DIR 66 USB20H_DATA2 67 USB20H_NXT 68 USB20H_DATA0 69 USB20H_DATA1 70 USB20H_STP 71 USB20H_DATA3 72 USB20H_DATA4 73 USB20H_DATA5 74 USB20H_DATA6 75 USB20H_DATA7 76 ETH_MDC 77 ETH_MDIO Functional Description 1. Power Supplies 1.1. Power Input The Genesys ZU power distribution network was designed to meet the specific requirements of Xilinx Zynq UltraScale+ MPSoCs and of the supported peripheral devices.
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When the board is turned on, the 12V input voltage provided by the bundled PCIe ATX supply is filtered and fed to the series MOSFETs of the protection circuit. The LM5060 IC monitors the input voltage and the current drawn by the entire board. If an input overvoltage/undervoltage or an overcurrent condition is detected, the LM5060 isolates the VCC12V0 net from the external supply by turning off the series MOSFETs.
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VCC0V85_INT () VCC12V0 0.825V / 0.85V / 0.875V 11A FPGA Internals VTT0V6 VCC1V2_PSDDR 0.6V (0.49xVCC1V2_PSDDR0.02V… … 0.51xVCC1V2_PSDDR+0.02V) 1A DDR4 VTT VREF0V6 VCC1V2_PSDDR 0.6V (0.49xVCC1V2_PSDDR… … 0.51xVCC1V2_PSDDR) 0.01A DDR4 reference voltage 1.3. Power Sequencing The board is powered up by sliding the SW5 switch to the ON position.
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You need a JTAG programmer to connect into the JTAG chain of the Genesys ZU. There is an on-board USB-JTAG controller for which Vivado support is expected in version 2020.1. Until built-in Vivado support is available a Digilent JTAG-HS1 or JTAG-HS2 programming cable will be bundled with the kit. This cable connects to the 6-pin header J28 and is already supported by Vivado.
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2.5. Status LEDs The Genesys ZU has four status LEDs: 1. 2. 3. 4. ERR : it is asserted for accidental loss of power, a hardware error or an exception in the Platform Management Unit (PMU); STS : it is asserted in secure lockdown state; INIT : indicates the PL is initialized after the power-on reset (POR); DONE : it is asserted when the PL configuration is completed; 3. Main Memory Main memory is a single-slot populated DDR4 SODIMM, always upgradeable by the user.
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The Flash is also commonly used to store non-configuration data needed by the application. If doing this from a bare-metal application, the flash memory can be freely accessed using standalone libraries included with a Xilinx SDK BSP project. If doing this from a Petalinux generated embedded Linux system, the Flash can be partitioned as desired and mounted/accessed like a standard MTD block device. See the Petalinux and Xilinx SDK documentation for more information.
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Although the default power-up configuration of the PHY might be enough in most applications, the MDIO bus is available for management. The PHY is assigned the 5-bit address 01111 on the MDIO bus. With simple register read and write commands, status information can be read out or configuration changed. The TI PHY follows industry-standard register map for basic configuration.
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The micro Type-B connector J8 connects to an FTDI FT4232HQ USB bridge. It provides a JTAG interface for programming and debugging, one UART interface connected to the MPSoC and one UART interface connected to the Platform MCU. The UART interfaces are exposed as standard COM ports. Their exact designator is determined upon enumeration, but the first one will always connect to the MPSoC and the second one to the Platform MCU.
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7.5. MIPI/Pcam Ports The two MIPI/Pcam ports included on the Genesys ZU are 15-pin, 1 mm pitch, zero insertion force (ZIF) connectors designed specifically for attaching camera sensor modules to host systems. It builds on the Pcam connector standard introduced on the Digilent Zybo Z7, but allows for bi-directional D-PHY lanes thanks to direct I/O support in the UltraScale+ architecture.
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J13 socket implements a versatile expansion option for adding SSD (), WLAN, Bluetooth or WWAN modules to the Genesys ZU. It is compatible with PCI Express Mini card types F1/F2 (Full-Mini) and H1/H2 (Half-Mini) and mSATA card types Mini and Full size. Mechanical compatibility is assured by the relocatable stand-offs included with the board. Electrically, the SATA lane and the PCIe x1 lane share the same PS-GTR transceiver lane.
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Attachment detection is implemented by the Platform MCU and pod presence is communicated to the MPSoC over the SYZYGY_DETECTED signal. For now, it is up to the MPSoC to read the port's SYZYGY DNA and implement SmartVIO functionality by requesting a compatible voltage on the VADJ rail. SYZYGY DNA is accessible on branch 5 of the I2C multiplexer on the main I2C bus at address 0110000b. SYZYGY pods are NOT hot-swappable.
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Digilent produces a large collection of Pmod accessory boards that can attach to the Pmod ports to add ready-made functions like A/D’s, D/A’s, motor drivers, sensors, and other functions. The vivado-library and vivado-hierarchies repositories on the Digilent Github (https://github.com/Digilent/) contains pre-made IP cores for many of these Pmods that greatly reduce the work of integrating them into your project. See the Pmod-related tutorials on the Genesys ZU Resource Center for help using them.
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The tri-color LED () has three input signals that drive the cathodes of three smaller internal LEDs: one red, one blue, and one green. Driving the input signal corresponding to one of these colors low will illuminate the internal LED (). The input signals are driven by the Zynq PL through a transistor, which inverts the signals. Therefore, to light up the tri-color LED (), the corresponding PL pins need to be driven high.
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At board power-up, Platform MCU detects if a SYZYGY peripheral board (“Pod”) is connected to Genesys ZU and signals this to the FPGA. If a SYZYGY Pod was detected, the SYZYGY_DETECTEDN pin (H11) is driven LOW. Otherwise the pin is driven HIGH. If VADJ_AUTO pin (G10) from FPGA is LOW, the Platform MCU establishes the correct VADJ voltage value based on VADJ_LEVEL1 (AC13) and VADJ_LEVEL0 (AC14) input pins, regardless of whether a syzygy pod and/or FMC mezzanine module is connected. Table 10.2.1.
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Offset Register Name Size [bits] R/W 0x04 Measured Fan Speed 16 R FPGA Fan Speed value in rpm, as computed based on the fan feedback pin. Upon read, the low byte is received first.
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10.2.2. Bootloader Section In the program memory, along with the Firmware Application, there is a bootloader that launches the Application at power-up. 10.3. Fan Mounted on the MPSoC heatsink, there is a 12 V fan with a 4-pin header. It can automatically be controlled by the Platform MCU based on the MPSoC temperature or set to the fixed full speed. This option is controlled by JP2 and is user-selectable. Table 10.3.