User manual

Basys MX3™ Board Reference Manual
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Page 25 of 56
The following timing diagrams detail how write and read processes must be implemented. The essential difference
is the polarity of the DISP_RW signal (0 for write and 1 for read). For more detailed timing information, refer to the
KS0066U datasheet.
Figure 8.2. LCD write timing.
Figure 8.3. LCD read timing.
8.1 Connectivity
Name
PIC32 Pin
Description
DISP_RS
AN15/RPB15/OCFB/CTED6/PMA0/RB15
Register Select: High for Data Transfer,
Low for Instruction Transfer.
DISP_RW
RPD5/PMRD/RD5
Read/Write signal: High for Read
mode, Low for Write mode.
DISP_EN
RPD4/PMWR/RD4
Read/Write Enable: High for Read,
falling edge writes data
DB0
PMD0/RE0
Data bits 0 -7.
DB1
PMD1/RE1
DB2
AN20/PMD2/RE2
DB3
RPE3/CTPLS/PMD3/RE3
DB4
AN21/PMD4/RE4
DB5
AN22/RPE5/PMD5/RE5
DB6
AN23/PMD6/RE6
DB7
AN27/PMD7/RE7
Table 8.1. LCD connectivity.