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Data Sheet

ManualsBrandsDigilent ManualsFPGACmod A7-35T Breadboardable Artix-7 FPGA Module
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Cmod A7 Reference Manual
Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.
Page 9 of 10
7.1 DIP Digital I/O
The pins connected directly to the FPGA can be used as general purpose inputs or outputs. There are no series
resistors between the FPGA and the DIP pins, so care should be taken not to cause shorts or connect them to
voltages greater than allowed by the FPGA. The absolute maximum voltages for these pins are outlined in Table
7.1.
Absolute
Minimum
Voltage
Recommended
Minimum Operating
Voltage
Recommended
Maximum Operating
Voltage
Absolute
Maximum
Voltage
Powered from
USB or VU
-0.4 V
-0.2 V
3.4 V
3.75 V
Unpowered
-0.4 V
N/A
N/A
0.55 V
Table 7.1. DIP pin voltage ratings.
For more information on the electrical characteristics of the pins connected to the FPGA, see the Artix-7 datasheet
from Xilinx.
7.2 Analog Inputs
Pins 15 and 16 of the DIP connector are used as analog inputs to the XADC module of the FPGA. The FPGA expects
that the inputs range from 0-1V, so we use an external circuit to scale down the input voltage from 3.3V. This
circuit is shown in Fig. 7.2.1. This circuit allows the XACD module to accurately measure any voltage between 0V
and 3.3V (relative to GND on pin 25) that is applied to either of these pins.
Figure 7.2.1. Analog input circuit.
The XADC core within the Artix-7 is a dual-channel 12-bit analog-to-digital converter capable of operating at 1
MSPS. Either channel can be driven by any of the two auxiliary analog inputs connected to the DIP pins. The XADC
core is controlled and accessed from a user design via the Dynamic Reconfiguration Port (DRP). The DRP also
provides access to voltage monitors that are present on each of the FPGA’s power rails, and a temperature sensor
that is internal to the FPGA. For more information on using the XADC core, refer to the Xilinx document titled 7
Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-bit 1 MSPS Analog-to-Digital Converter. A demo
that uses the XADC core is available on the Cmod A7 resource center.