Datasheet

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.21) September 27, 2016 www.xilinx.com
Product Specification 8
DC Input and Output Levels
Values for V
IL
and V
IH
are recommended input voltages. Values for I
OL
and I
OH
are guaranteed over the recommended
operating conditions at the V
OL
and V
OH
test points. Only selected standards are tested. These are chosen to ensure that all
standards meet their specifications. The selected standards are tested at a minimum V
CCO
with the respective V
OL
and V
OH
voltage levels shown. Other standards are sample tested.
Table 7: Power Supply Ramp Time
Symbol Description Conditions Min Max Units
T
VCCINT
Ramp time from GND to 90% of V
CCINT
0.2 50 ms
T
VCCO
Ramp time from GND to 90% of V
CCO
0.2 50 ms
T
VCCAUX
Ramp time from GND to 90% of V
CCAUX
0.2 50 ms
T
VCCBRAM
Ramp time from GND to 90% of V
CCBRAM
0.2 50 ms
T
VCCO2VCCAUX
Allowed time per power cycle for V
CCO
– V
CCAUX
> 2.625V
T
J
= 125°C
(1)
–300
msT
J
= 100°C
(1)
–500
T
J
= 85°C
(1)
–800
T
MGTAVCC
Ramp time from GND to 90% of V
MGTAVCC
0.2 50 ms
T
MGTAVTT
Ramp time from GND to 90% of V
MGTAVTT
0.2 50 ms
Notes:
1. Based on 240,000 power cycles with nominal V
CCO
of 3.3V or 36,500 power cycles with worst case V
CCO
of 3.465V.
Table 8: SelectIO DC Input and Output Levels
(1)(2)
I/O Standard
V
IL
V
IH
V
OL
V
OH
I
OL
I
OH
V, Min V, Max V, Min V, Max V, Max V, Min mA, Max mA, Min
HSTL_I –0.300 V
REF
– 0.100 V
REF
+ 0.100 V
CCO
+ 0.300 0.400 V
CCO
– 0.400 8.00 –8.00
HSTL_I_18 –0.300 V
REF
– 0.100 V
REF
+ 0.100 V
CCO
+ 0.300 0.400 V
CCO
– 0.400 8.00 –8.00
HSTL_II –0.300 V
REF
– 0.100 V
REF
+ 0.100 V
CCO
+ 0.300 0.400 V
CCO
– 0.400 16.00 –16.00
HSTL_II_18 –0.300 V
REF
– 0.100 V
REF
+ 0.100 V
CCO
+ 0.300 0.400 V
CCO
– 0.400 16.00 –16.00
HSUL_12 –0.300 V
REF
– 0.130 V
REF
+ 0.130 V
CCO
+ 0.300 20% V
CCO
80% V
CCO
0.10 –0.10
LVCMOS12 –0.300 35% V
CCO
65% V
CCO
V
CCO
+ 0.300 0.400 V
CCO
–0.400 Note 3 Note 3
LVCMOS15 –0.300 35% V
CCO
65% V
CCO
V
CCO
+ 0.300 25% V
CCO
75% V
CCO
Note 4 Note 4
LVCMOS18 –0.300 35% V
CCO
65% V
CCO
V
CCO
+ 0.300 0.450 V
CCO
–0.450 Note 5 Note 5
LVCMOS25 –0.300 0.7 1.700 V
CCO
+ 0.300 0.400 V
CCO
–0.400 Note 4 Note 4
LVCMOS33 –0.300 0.8 2.000 3.450 0.400 V
CCO
–0.400 Note 4 Note 4
LVTTL –0.300 0.8 2.000 3.450 0.400 2.400 Note 5 Note 5
MOBILE_DDR –0.300 20% V
CCO
80% V
CCO
V
CCO
+ 0.300 10% V
CCO
90% V
CCO
0.10 –0.10
PCI33_3 –0.400 30% V
CCO
50% V
CCO
V
CCO
+ 0.500 10% V
CCO
90% V
CCO
1.50 –0.50
SSTL135 –0.300 V
REF
– 0.090 V
REF
+ 0.090 V
CCO
+0.300 V
CCO
/2–0.150 V
CCO
/2 + 0.150 13.00 –13.00
SSTL135_R –0.300 V
REF
– 0.090 V
REF
+ 0.090 V
CCO
+0.300 V
CCO
/2–0.150 V
CCO
/2 + 0.150 8.90 –8.90
SSTL15 –0.300 V
REF
– 0.100 V
REF
+ 0.100 V
CCO
+0.300 V
CCO
/2–0.175 V
CCO
/2 + 0.175 13.00 –13.00
SSTL15_R –0.300 V
REF
– 0.100 V
REF
+ 0.100 V
CCO
+0.300 V
CCO
/2–0.175 V
CCO
/2 + 0.175 8.90 –8.90
SSTL18_I –0.300 V
REF
– 0.125 V
REF
+ 0.125 V
CCO
+0.300 V
CCO
/2–0.470 V
CCO
/2 + 0.470 8.00 –8.00