Datasheet

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.21) September 27, 2016 www.xilinx.com
Product Specification 7
Power-On/Off Power Supply Sequencing
The recommended power-on sequence is V
CCINT
, V
CCBRAM
, V
CCAUX
, and V
CCO
to achieve minimum current draw and ensure
that the I/Os are 3-stated at power-on. The recommended power-off sequence is the reverse of the power-on sequence. If
V
CCINT
and V
CCBRAM
have the same recommended voltage levels then both can be powered by the same supply and ramped
simultaneously. If V
CCAUX
and V
CCO
have the same recommended voltage levels then both can be powered by the same
supply and ramped simultaneously.
For V
CCO
voltages of 3.3V in HR I/O banks and configuration bank 0:
• The voltage difference between V
CCO
and V
CCAUX
must not exceed 2.625V for longer than T
VCCO2VCCAUX
for each
power-on/off cycle to maintain device reliability levels.
•The T
VCCO2VCCAUX
time can be allocated in any percentage between the power-on and power-off ramps.
The recommended power-on sequence to achieve minimum current draw for the GTP transceivers is V
CCINT
, V
MGTAVCC
,
V
MGTAVTT
OR V
MGTAVCC
, V
CCINT
, V
MGTAVTT
. Both V
MGTAVCC
and V
CCINT
can be ramped simultaneously. The recommended
power-off sequence is the reverse of the power-on sequence to achieve minimum current draw.
If these recommended sequences are not met, current drawn from V
MGTAVTT
can be higher than specifications during power-
up and power-down.
•When V
MGTAVTT
is powered before V
MGTAVCC
and V
MGTAVTT
–V
MGTAVCC
> 150 mV and V
MGTAVCC
<0.7V, the V
MGTAVTT
current draw can increase by 460 mA per transceiver during V
MGTAVCC
ramp up. The duration of the current draw can be
up to 0.3 x T
MGTAVCC
(ramp time from GND to 90% of V
MGTAVCC
). The reverse is true for power-down.
•When V
MGTAVTT
is powered before V
CCINT
and V
MGTAVTT
–V
CCINT
> 150 mV and V
CCINT
<0.7V, the V
MGTAVTT
current
draw can increase by 50 mA per transceiver during V
CCINT
ramp up. The duration of the current draw can be up to
0.3 x T
VCCINT
(ramp time from GND to 90% of V
CCINT
). The reverse is true for power-down.
There is no recommended sequence for supplies not shown.
Table 6 shows the minimum current, in addition to I
CCQ
, that is required by Artix-7 devices for proper power-on and
configuration. If the current minimums shown in Table 5 and Table 6 are met, the device powers on after all four supplies
have passed through their power-on reset threshold voltages. The FPGA must not be configured until after V
CCINT
is applied.
Once initialized and configured, use the Xilinx Power Estimator (XPE) tools to estimate current drain on these supplies.
Table 6: Power-On Current for Artix-7 Devices
Device I
CCINTMIN
I
CCAUXMIN
I
CCOMIN
I
CCBRAMMIN
Units
XC7A12T I
CCINTQ
+120 I
CCAUXQ
+40 I
CCOQ
+ 40 mA per bank I
CCBRAMQ
+60 mA
XC7A15T I
CCINTQ
+120 I
CCAUXQ
+40 I
CCOQ
+ 40 mA per bank I
CCBRAMQ
+60 mA
XC7A25T I
CCINTQ
+120 I
CCAUXQ
+40 I
CCOQ
+ 40 mA per bank I
CCBRAMQ
+60 mA
XC7A35T I
CCINTQ
+120 I
CCAUXQ
+40 I
CCOQ
+ 40 mA per bank I
CCBRAMQ
+60 mA
XC7A50T I
CCINTQ
+120 I
CCAUXQ
+40 I
CCOQ
+ 40 mA per bank I
CCBRAMQ
+60 mA
XC7A75T I
CCINTQ
+170 I
CCAUXQ
+40 I
CCOQ
+ 40 mA per bank I
CCBRAMQ
+60 mA
XC7A100T I
CCINTQ
+170 I
CCAUXQ
+40 I
CCOQ
+ 40 mA per bank I
CCBRAMQ
+60 mA
XC7A200T I
CCINTQ
+340 I
CCAUXQ
+50 I
CCOQ
+ 40 mA per bank I
CCBRAMQ
+80 mA
XA7A15T I
CCINTQ
+120 I
CCAUXQ
+40 I
CCOQ
+ 40 mA per bank I
CCBRAMQ
+60 mA
XA7A35T I
CCINTQ
+120 I
CCAUXQ
+40 I
CCOQ
+ 40 mA per bank I
CCBRAMQ
+60 mA
XA7A50T I
CCINTQ
+120 I
CCAUXQ
+40 I
CCOQ
+ 40 mA per bank I
CCBRAMQ
+60 mA
XA7A75T I
CCINTQ
+170 I
CCAUXQ
+40 I
CCOQ
+ 40 mA per bank I
CCBRAMQ
+60 mA
XA7A100T I
CCINTQ
+170 I
CCAUXQ
+40 I
CCOQ
+ 40 mA per bank I
CCBRAMQ
+60 mA
XQ7A50T I
CCINTQ
+120 I
CCAUXQ
+40 I
CCOQ
+ 40 mA per bank I
CCBRAMQ
+60 mA
XQ7A100T I
CCINTQ
+170 I
CCAUXQ
+40 I
CCOQ
+ 40 mA per bank I
CCBRAMQ
+60 mA
XQ7A200T I
CCINTQ
+340 I
CCAUXQ
+50 I
CCOQ
+ 40 mA per bank I
CCBRAMQ
+80 mA