Datasheet

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.21) September 27, 2016 www.xilinx.com
Product Specification 59
eFUSE Programming Conditions
Table 67 lists the programming conditions specifically for eFUSE. For more information, see 7 Series FPGA Configuration User
Guide (UG470
).
Revision History
The following table shows the revision history for this document:
Device DNA Access Port
F
DNACK
DNA access port (DNA_PORT) 100.00 100.00 100.00 100.00 70.00 MHz, Max
Notes:
1. To support longer delays in configuration, use the design solutions described in 7 Series FPGA Configuration User Guide (UG470).
2. Only during configuration, the last edge is determined by a weak pull-up/pull-down resistor in the I/O.
Table 67: eFUSE Programming Conditions
(1)
Symbol Description Min Typ Max Units
I
FS
V
CCAUX
supply current – – 115 mA
T
j
Temperature range 15 – 125 °C
Notes:
1. The FPGA must not be configured during eFUSE programming.
Date Version Description
09/26/2011 1.0 Initial Xilinx release.
11/07/2011 1.1 Revised the V
OCM
specification in Table 11. Updated the AC Switching Characteristics based upon the
ISE 13.3 software v1.02 speed specification throughout document including Table 13 and Table 14.
Added MMCM_T
FBDELAY
while adding MMCM_ to the symbol names of a few specifications in
Table 37 and PLL to the symbol names in Table 38. In Table 39 through Table 46, updated the pin-to-
pin description with the SSTL15 standard. Updated units in Table 46.
02/13/2012 1.2 Updated the Artix-7 family of devices listed throughout the entire data sheet. Updated the AC Switching
Characteristics based upon the ISE 13.4 software v1.03 for the -3, -2, and -1 speed grades and v1.00
for the -2L speed grade.
Updated summary description on page 1. In Table 2, revised V
CCO
for the 3.3V HR I/O banks and
updated T
j
. Updated the notes in Table 5. Added MGTAVCC and MGTAVTT power supply ramp times
to Table 7. Rearranged Table 8, added Mobile_DDR, HSTL_I_18, HSTL_II_18, HSUL_12,
SSTL135_R, SSTL15_R, and SSTL12 and removed DIFF_SSTL135, DIFF_SSTL18_I,
DIFF_SSTL18_II, DIFF_HSTL_I, and DIFF_HSTL_II. Added Table 9 and Table 10. Revised the
specifications in Table 11. Revised V
IN
in Table 50. Updated the eFUSE Programming Conditions
section and removed the endurance table. Added the table. Revised F
TXIN
and F
RXIN
in Table 56.
Revised I
CCADC
and updated Note 1 in Table 65. Revised DDR LVDS transmitter data width in
Table 15. Removed notes from Table 27 as they are no longer applicable. Updated specifications in
Table 66. Updated Note 1 in Table 36.
Table 66: Configuration Switching Characteristics (Cont’d)
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1LI -2LE