Datasheet

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.21) September 27, 2016 www.xilinx.com
Product Specification 58
Internal Configuration Access Port
F
ICAPCK
Internal configuration access port (ICAPE2)
clock frequency
100.00 100.00 100.00 100.00 70.00 MHz, Max
Master/Slave Serial Mode Programming Switching
T
DCCK
/
T
CCKD
DIN setup/hold 4.00/0.00 4.00/0.00 4.00/0.00 4.00/0.00 5.00/0.00 ns, Min
T
CCO
DOUT clock to out 8.00 8.00 8.00 8.00 9.00 ns, Max
SelectMAP Mode Programming Switching
T
SMDCCK
/
T
SMCCKD
D[31:00] setup/hold 4.00/0.00 4.00/0.00 4.00/0.00 4.00/0.00 4.50/0.00 ns, Min
T
SMCSCCK
/
T
SMCCKCS
CSI_B setup/hold 4.00/0.00 4.00/0.00 4.00/0.00 4.00/0.00 5.00/0.00 ns, Min
T
SMWCCK
/
T
SMCCKW
RDWR_B setup/hold 10.00/0.00 10.00/0.00 10.00/0.00 10.00/0.00 12.00/0.00 ns, Min
T
SMCKCSO
CSO_B clock to out (330 Ω pull-up resistor
required)
7.00 7.00 7.00 7.00 8.00 ns, Max
T
SMCO
D[31:00] clock to out in readback 8.00 8.00 8.00 8.00 10.00 ns, Max
F
RBCCK
Readback frequency 100.00 100.00 100.00 100.00 70.00 MHz, Max
Boundary-Scan Port Timing Specifications
T
TAPTCK
/
T
TCKTAP
TMS and TDI setup/hold 3.00/2.00 3.00/2.00 3.00/2.00 3.00/2.00 3.00/2.00 ns, Min
T
TCKTDO
TCK falling edge to TDO output 7.00 7.00 7.00 7.00 8.50 ns, Max
F
TCK
TCK frequency 66.00 66.00 66.00 66.00 50.00 MHz, Max
BPI Flash Master Mode Programming Switching
T
BPICCO
(2)
A[28:00], RS[1:0], FCS_B, FOE_B, FWE_B,
ADV_B clock to out
8.50 8.50 8.50 8.50 10.00 ns, Max
T
BPIDCC
/
T
BPICCD
D[15:00] setup/hold 4.00/0.00 4.00/0.00 4.00/0.00 4.00/0.00 4.50/0.00 ns, Min
SPI Flash Master Mode Programming Switching
T
SPIDCC
/
T
SPICCD
D[03:00] setup/hold 3.00/0.00 3.00/0.00 3.00/0.00 3.00/0.00 3.00/0.00 ns, Min
T
SPICCM
MOSI clock to out 8.00 8.00 8.00 8.00 9.00 ns, Max
T
SPICCFC
FCS_B clock to out 8.00 8.00 8.00 8.00 9.00 ns, Max
STARTUPE2 Ports
T
USRCCLKO
STARTUPE2 USRCCLKO input to CCLK output 0.50/6.00 0.50/6.70 0.50/7.50 0.50/7.50 0.50/7.50 ns,
Min/Max
F
CFGMCLK
STARTUPE2 CFGMCLK output frequency 65.00 65.00 65.00 65.00 65.00 MHz, Typ
F
CFGMCLKTOL
STARTUPE2 CFGMCLK output frequency
tolerance
±50 ±50 ±50 ±50 ±50 %, Max
Table 66: Configuration Switching Characteristics (Cont’d)
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1LI -2LE