Datasheet

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.21) September 27, 2016 www.xilinx.com
Product Specification 57
Configuration Switching Characteristics
XADC Reference
(5)
External Reference V
REFP
Externally supplied reference voltage 1.20 1.25 1.30 V
On-Chip Reference Ground V
REFP
pin to AGND,
–40°C ≤ T
j
≤ 100°C
1.2375 1.25 1.2625 V
Ground V
REFP
pin to AGND,
–55°C ≤ T
j
< –40°C; 100°C < T
j
≤ 125°C
1.225 1.25 1.275 V
Notes:
1. Offset and gain errors are removed by enabling the XADC automatic gain calibration feature. The values are specified for when this feature
is enabled.
2. Only specified for bitstream option XADCEnhancedLinearity = ON.
3. See the ADC chapter in the 7 Series FPGAs and Zynq-7000 AP SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter (UG480
) for a
detailed description.
4. See the Timing chapter in the 7 Series FPGAs and Zynq-7000 AP SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter (UG480
) for
a detailed description.
5. Any variation in the reference voltage from the nominal V
REFP
= 1.25V and V
REFN
= 0V will result in a deviation from the ideal transfer
function. This also impacts the accuracy of the internal sensor measurements (i.e., temperature and power supply). However, for external
ratiometric type applications allowing reference to vary by ±4% is permitted.
Table 66: Configuration Switching Characteristics
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1LI -2LE
Power-up Timing Characteristics
T
PL
(1)
Program latency 5.00 5.00 5.00 5.00 5.00 ms, Max
T
POR
(1)
Power-on reset (50 ms ramp rate time) 10/50 10/50 10/50 10/50 10/50 ms, Min/Max
Power-on reset (1 ms ramp rate time) 10/35 10/35 10/35 10/35 10/35 ms, Min/Max
T
PROGRAM
Program pulse width 250.00 250.00 250.00 250.00 250.00 ns, Min
CCLK Output (Master Mode)
T
ICCK
Master CCLK output delay 150.00 150.00 150.00 150.00 150.00 ns, Min
T
MCCKL
Master CCLK clock Low time duty cycle 40/60 40/60 40/60 40/60 40/60 %, Min/Max
T
MCCKH
Master CCLK clock High time duty cycle 40/60 40/60 40/60 40/60 40/60 %, Min/Max
F
MCCK
Master CCLK frequency 100.00 100.00 100.00 100.00 70.00 MHz, Max
Master CCLK frequency for AES encrypted x16 50.00 50.00 50.00 50.00 35.00 MHz, Max
F
MCCK_START
Master CCLK frequency at start of configuration 3.00 3.00 3.00 3.00 3.00 MHz, Typ
F
MCCKTOL
Frequency tolerance, master mode with respect
to nominal CCLK
±50 ±50 ±50 ±50 ±50 %, Max
CCLK Input (Slave Modes)
T
SCCKL
Slave CCLK clock minimum Low time 2.50 2.50 2.50 2.50 2.50 ns, Min
T
SCCKH
Slave CCLK clock minimum High time 2.50 2.50 2.50 2.50 2.50 ns, Min
F
SCCK
Slave CCLK frequency 100.00 100.00 100.00 100.00 70.00 MHz, Max
EMCCLK Input (Master Mode)
T
EMCCKL
External master CCLK Low time 2.50 2.50 2.50 2.50 2.50 ns, Min
T
EMCCKH
External master CCLK High time 2.50 2.50 2.50 2.50 2.50 ns, Min
F
EMCCK
External master CCLK frequency 100.00 100.00 100.00 100.00 70.00 MHz, Max
Table 65: XADC Specifications (Cont’d)
Parameter Symbol Comments/Conditions Min Typ Max Units