Datasheet

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.21) September 27, 2016 www.xilinx.com
Product Specification 54
GTP Transceiver Protocol Jitter Characteristics
For Table 59 through Table 63, the 7 Series FPGAs GTP Transceiver User Guide (UG482) contains recommended settings for
optimal usage of protocol specific characteristics.
Table 59: Gigabit Ethernet Protocol Characteristics
Description Line Rate (Mb/s) Min Max Units
Gigabit Ethernet Transmitter Jitter Generation
Total transmitter jitter (T_TJ) 1250 – 0.24 UI
Gigabit Ethernet Receiver High Frequency Jitter Tolerance
Total receiver jitter tolerance 1250 0.749 – UI
Table 60: XAUI Protocol Characteristics
Description Line Rate (Mb/s) Min Max Units
XAUI Transmitter Jitter Generation
Total transmitter jitter (T_TJ) 3125 – 0.35 UI
XAUI Receiver High Frequency Jitter Tolerance
Total receiver jitter tolerance 3125 0.65 – UI
Table 61: PCI Express Protocol Characteristics
(1)
Standard Description Line Rate (Mb/s) Min Max Units
PCI Express Transmitter Jitter Generation
PCI Express Gen 1 Total transmitter jitter 2500 – 0.25 UI
PCI Express Gen 2 Total transmitter jitter 5000 – 0.25 UI
PCI Express Receiver High Frequency Jitter Tolerance
PCI Express Gen 1 Total receiver jitter tolerance 2500 0.65 – UI
PCI Express Gen 2
(2)
Receiver inherent timing error
5000
0.40 – UI
Receiver inherent deterministic timing error 0.30 – UI
Notes:
1. Tested per card electromechanical (CEM) methodology.
2. Using common REFCLK.
Table 62: CEI-6G Protocol Characteristics
Description Line Rate (Mb/s) Interface Min Max Units
CEI-6G Transmitter Jitter Generation
Total transmitter jitter
(1)
4976–6375 CEI-6G-SR – 0.3 UI
CEI-6G Receiver High Frequency Jitter Tolerance
Total receiver jitter tolerance
(1)
4976–6375 CEI-6G-SR 0.6 – UI
Notes:
1. Tested at most commonly used line rate of 6250 Mb/s using 390.625 MHz reference clock.