Datasheet

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.21) September 27, 2016 www.xilinx.com
Product Specification 52
Table 57: GTP Transceiver Transmitter Switching Characteristics
Symbol Description Condition Min Typ Max Units
F
GTPTX
Serial data rate range 0.500 – F
GTPMAX
Gb/s
T
RTX
TX rise time 20%–80% – 50 – ps
T
FTX
TX fall time 80%–20% – 50 – ps
T
LLSKEW
TX lane-to-lane skew
(1)
– – 500 ps
V
TXOOBVDPP
Electrical idle amplitude – – 20 mV
T
TXOOBTRANSITION
Electrical idle transition time – – 140 ns
TJ
6.6
Total Jitter
(2)(3)
6.6 Gb/s
– – 0.30 UI
DJ
6.6
Deterministic Jitter
(2)(3)
– – 0.15 UI
TJ
5.0
Total Jitter
(2)(3)
5.0 Gb/s
– – 0.30 UI
DJ
5.0
Deterministic Jitter
(2)(3)
– – 0.15 UI
TJ
4.25
Total Jitter
(2)(3)
4.25 Gb/s
– – 0.30 UI
DJ
4.25
Deterministic Jitter
(2)(3)
– – 0.15 UI
TJ
3.75
Total Jitter
(2)(3)
3.75 Gb/s
– – 0.30 UI
DJ
3.75
Deterministic Jitter
(2)(3)
– – 0.15 UI
TJ
3.2
Total Jitter
(2)(3)
3.20 Gb/s
(4)
––0.2UI
DJ
3.2
Deterministic Jitter
(2)(3)
––0.1UI
TJ
3.2L
Total Jitter
(2)(3)
3.20 Gb/s
(5)
– – 0.32 UI
DJ
3.2L
Deterministic Jitter
(2)(3)
– – 0.16 UI
TJ
2.5
Total Jitter
(2)(3)
2.5 Gb/s
(6)
– – 0.20 UI
DJ
2.5
Deterministic Jitter
(2)(3)
– – 0.08 UI
TJ
1.25
Total Jitter
(2)(3)
1.25 Gb/s
(7)
– – 0.15 UI
DJ
1.25
Deterministic Jitter
(2)(3)
– – 0.06 UI
TJ
500
Total Jitter
(2)(3)
500 Mb/s
––0.1UI
DJ
500
Deterministic Jitter
(2)(3)
– – 0.03 UI
Notes:
1. Using same REFCLK input with TX phase alignment enabled for up to four consecutive transmitters (one fully populated GTP Quad).
2. Using PLL[0/1]_FBDIV = 2, 20-bit internal data width. These values are NOT intended for protocol specific compliance determinations.
3. All jitter values are based on a bit-error ratio of 1e
-12
.
4. PLL frequency at 3.2 GHz and TXOUT_DIV = 2.
5. PLL frequency at 1.6 GHz and TXOUT_DIV = 1.
6. PLL frequency at 2.5 GHz and TXOUT_DIV = 2.
7. PLL frequency at 2.5 GHz and TXOUT_DIV = 4.