Datasheet

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.21) September 27, 2016 www.xilinx.com
Product Specification 51
Table 55: GTP Transceiver PLL/Lock Time Adaptation
Symbol Description Conditions
All Speed Grades
Units
Min Typ Max
T
LOCK
Initial PLL lock – – 1 ms
T
DLOCK
Clock recovery phase acquisition and
adaptation time.
After the PLL is locked to the
reference clock, this is the time it
takes to lock the clock data
recovery (CDR) to the data
present at the input.
– 50,000 2.3 x10
6
UI
Table 56: GTP Transceiver User Clock Switching Characteristics
(1)
Symbol Description Conditions
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1LI -2LE
F
TXOUT
TXOUTCLK maximum frequency 412.500 412.500 234.375 234.375 234.375 MHz
F
RXOUT
RXOUTCLK maximum frequency 412.500 412.500 234.375 234.375 234.375 MHz
F
TXIN
TXUSRCLK maximum frequency 16-bit data path 412.500 412.500 234.375 234.375 234.375 MHz
F
RXIN
RXUSRCLK maximum frequency 16-bit data path 412.500 412.500 234.375 234.375 234.375 MHz
F
TXIN2
TXUSRCLK2 maximum frequency 16-bit data path 412.500 412.500 234.375 234.375 234.375 MHz
F
RXIN2
RXUSRCLK2 maximum frequency 16-bit data path 412.500 412.500 234.375 234.375 234.375 MHz
Notes:
1. Clocking must be implemented as described in 7 Series FPGAs GTP Transceiver User Guide (UG482).