Datasheet

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.21) September 27, 2016 www.xilinx.com
Product Specification 50
GTP Transceiver Switching Characteristics
Consult 7 Series FPGAs GTP Transceiver User Guide (UG482) for further information.
Table 52: GTP Transceiver Performance
Symbol Description
Output
Divider
Speed Grade
Units
-3 (1.0V)
-2 (1.0V)
-2LE (1.0V)
-1 (1.0V)
-1LI (0.95V)
-1Q (1.0V)
-1M (1.0V)
-2LE (0.9V)
Package Type
FF
FB
SB
FG
FT
CS
CP
FF
FB
SB
RB
RS
FG
FT
CS
CP
FF
FB
SB
RB
RS
FG
FT
CS
CP
FF
FB
SB
FG
FT
CS
CP
F
GTPMAX
Maximum GTP transceiver data rate 6.6 6.25 6.6 6.25 3.75 3.75 3.75 3.75 Gb/s
F
GTPMIN
Minimum GTP transceiver data rate 0.500 0.500 0.500 0.500 0.500 0.500 0.500 0.500 Gb/s
F
GTPRANGE
PLL line rate range
1 3.2–6.6 3.2–6.6 3.2–3.75 3.2–3.75 Gb/s
2 1.6–3.3 1.6–3.3 1.6–3.2 1.6–3.2 Gb/s
4 0.8–1.65 0.8–1.65 0.8–1.6 0.8–1.6 Gb/s
8 0.5–0.825 0.5–0.825 0.5–0.8 0.5–0.8 Gb/s
F
GTPPLLRANGE
GTP transceiver PLL frequency
range
1.6–3.3 1.6–3.3 1.6–3.3 1.6–3.3 GHz
Table 53: GTP Transceiver Dynamic Reconfiguration Port (DRP) Switching Characteristics
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1LI -2LE
F
GTPDRPCLK
GTPDRPCLK maximum frequency 175 175 156 156 125 MHz
Table 54: GTP Transceiver Reference Clock Switching Characteristics
Symbol Description Conditions
All Speed Grades
Units
Min Typ Max
F
GCLK
Reference clock frequency range 60 – 660 MHz
T
RCLK
Reference clock rise time 20% – 80% – 200 – ps
T
FCLK
Reference clock fall time 80% – 20% – 200 – ps
T
DCREF
Reference clock duty cycle Transceiver PLL only 40 – 60 %
X-Ref Target - Figure 5
Figure 5: Reference Clock Timing Parameters
ds181_03_062811
80%
20%
T
FCLK
T
RCLK