Datasheet

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.21) September 27, 2016 www.xilinx.com
Product Specification 47
Additional Package Parameter Guidelines
The parameters in this section provide the necessary values for calculating timing budgets for Artix-7 FPGA clock transmitter
and receiver data-valid windows.
T
SAMP_BUFIO
Sampling error at receiver pins using
BUFIO
(2)
0.35 0.40 0.46 0.46 0.46 0.46 ns
Notes:
1. This parameter indicates the total sampling error of the Artix-7 FPGAs DDR input registers, measured across voltage, temperature, and
process. The characterization methodology uses the MMCM to capture the DDR input registers’ edges of operation. These measurements
include:
- CLK0 MMCM jitter
- MMCM accuracy (phase offset)
- MMCM phase shift resolution
These measurements do not include package or clock tree skew.
2. This parameter indicates the total sampling error of the Artix-7 FPGAs DDR input registers, measured across voltage, temperature, and
process. The characterization methodology uses the BUFIO clock network and IDELAY to capture the DDR input registers’ edges of
operation. These measurements do not include package or clock tree skew.
Table 49: Package Skew
Symbol Description Device Package Value Units
T
PKGSKEW
Package skew
(1)
XC7A12T
CPG236 ps
CSG325 ps
XC7A15T
CPG236 48 ps
CSG324 104 ps
CSG325 142 ps
FTG256 98 ps
FGG484 97 ps
XC7A25T
CPG236 ps
CSG325 ps
XC7A35T
CPG236 48 ps
CSG324 104 ps
CSG325 142 ps
FTG256 98 ps
FGG484 97 ps
XC7A50T
CPG236 48 ps
CSG324 104 ps
CSG325 142 ps
FTG256 98 ps
FGG484 97 ps
XC7A75T
CSG324 113 ps
FTG256 120 ps
FGG484 144 ps
FGG676 153 ps
Table 48: Sample Window (Cont’d)
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1M/-1Q -1LI -2LE