Datasheet

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.21) September 27, 2016 www.xilinx.com
Product Specification 46
Table 46: Clock-Capable Clock Input Setup and Hold With PLL
Symbol Description Device
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1M/-1Q -1LI -2LE
Input Setup and Hold Time Relative to Clock-Capable Clock Input Signal for SSTL15 Standard.
(1)
T
PSPLLCC
/
T
PHPLLCC
No delay clock-capable
clock input and IFF
(2)
with PLL
XC7A12T 2.68/–0.19 3.04/–0.19 3.63/–0.19 N/A 3.63/–0.19 ns
XC7A15T 2.77/–0.20 3.15/–0.20 3.77/–0.20 N/A 3.77/–0.20 2.46/–0.59 ns
XC7A25T 2.68/–0.19 3.04/–0.19 3.63/–0.19 N/A 3.63/–0.19 ns
XC7A35T 2.77/–0.20 3.15/–0.20 3.77/–0.20 N/A 3.77/–0.20 2.46/–0.59 ns
XC7A50T 2.77/–0.20 3.15/–0.20 3.77/–0.20 N/A 3.77/–0.20 2.46/–0.59 ns
XC7A75T 2.78/–0.20 3.15/–0.20 3.78/–0.20 N/A 3.78/–0.20 2.47/–0.59 ns
XC7A100T 2.78/–0.20 3.15/–0.20 3.78/–0.20 N/A 3.78/–0.20 2.47/–0.59 ns
XC7A200T 2.91/–0.21 3.29/–0.21 3.94/–0.21 N/A 3.94/–0.21 2.64/–0.62 ns
XA7A15T N/A 3.15/–0.20 3.77/–0.20 3.77/–0.20 N/A N/A ns
XA7A35T N/A 3.15/–0.20 3.77/–0.20 3.77/–0.20 N/A N/A ns
XA7A50T N/A 3.15/–0.20 3.77/–0.20 3.77/–0.20 N/A N/A ns
XA7A75T N/A 3.15/–0.20 3.78/–0.20 3.78/–0.20 N/A N/A ns
XA7A100T N/A 3.15/–0.20 3.78/–0.20 3.78/–0.20 N/A N/A ns
XQ7A50T N/A 3.15/–0.20 3.77/–0.20 3.77/–0.20 3.77/–0.20 N/A ns
XQ7A100T N/A 3.15/–0.20 3.78/–0.20 3.78/–0.20 3.78/–0.20 N/A ns
XQ7A200T N/A 3.29/–0.21 3.94/–0.21 3.94/–0.21 3.94/–0.21 N/A ns
Notes:
1. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the
global clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the global
clock input signal using the fastest process, lowest temperature, and highest voltage.
2. IFF = Input flip-flop or latch
3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
Table 47: Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin Using BUFIO
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1M/-1Q -1LI -2LE
Input Setup and Hold Time Relative to a Forwarded Clock Input Pin Using BUFIO for SSTL15 Standard.
T
PSCS
/T
PHCS
Setup and hold of I/O clock –0.38/1.31 –0.38/1.46 –0.38/1.76 –0.38/1.76 –0.38/1.76 –0.16/1.89 ns
Table 48: Sample Window
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1M/-1Q -1LI -2LE
T
SAMP
Sampling error at receiver pins
(1)
0.59 0.64 0.70 0.70 0.70 0.70 ns