Datasheet

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.21) September 27, 2016 www.xilinx.com
Product Specification 45
Table 45: Clock-Capable Clock Input Setup and Hold With MMCM
Symbol Description Device
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1M/-1Q -1LI -2LE
Input Setup and Hold Time Relative to Global Clock Input Signal for SSTL15 Standard.
(1)
T
PSMMCMCC
/
T
PHMMCMCC
No delay clock-
capable clock input
and IFF
(2)
with
MMCM
XC7A12T 2.37/–0.61 2.69/–0.61 3.21/–0.61 N/A 3.21/–0.61 ns
XC7A15T 2.46/–0.62 2.80/–0.62 3.35/–0.62 N/A 3.35/–0.62 2.14/–0.48 ns
XC7A25T 2.37/–0.61 2.69/–0.61 3.21/–0.61 N/A 3.21/–0.61 ns
XC7A35T 2.46/–0.62 2.80/–0.62 3.35/–0.62 N/A 3.35/–0.62 2.14/–0.48 ns
XC7A50T 2.46/–0.62 2.80/–0.62 3.35/–0.62 N/A 3.35/–0.62 2.14/–0.48 ns
XC7A75T 2.47/–0.62 2.81/–0.62 3.36/–0.62 N/A 3.36/–0.62 2.15/–0.48 ns
XC7A100T 2.47/–0.62 2.81/–0.62 3.36/–0.62 N/A 3.36/–0.62 2.15/–0.48 ns
XC7A200T 2.59/–0.63 2.95/–0.63 3.52/–0.63 N/A 3.52/–0.63 2.32/–0.51 ns
XA7A15T N/A 2.80/–0.62 3.35/–0.62 3.35/–0.62 N/A N/A ns
XA7A35T N/A 2.80/–0.62 3.35/–0.62 3.35/–0.62 N/A N/A ns
XA7A50T N/A 2.80/–0.62 3.35/–0.62 3.35/–0.62 N/A N/A ns
XA7A75T N/A 2.81/–0.62 3.36/–0.62 3.36/–0.62 N/A N/A ns
XA7A100T N/A 2.81/–0.62 3.36/–0.62 3.36/–0.62 N/A N/A ns
XQ7A50T N/A 2.80/–0.62 3.35/–0.62 3.35/–0.62 3.35/–0.62 N/A ns
XQ7A100T N/A 2.81/–0.62 3.36/–0.62 3.36/–0.62 3.36/–0.62 N/A ns
XQ7A200T N/A 2.95/–0.63 3.52/–0.63 3.52/–0.63 3.52/–0.63 N/A ns
Notes:
1. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the
global clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the global
clock input signal using the fastest process, lowest temperature, and highest voltage.
2. IFF = Input flip-flop or latch
3. Use IBIS to determine any duty-cycle distortion incurred using various standards.