Datasheet

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.21) September 27, 2016 www.xilinx.com
Product Specification 43
Table 42: Clock-Capable Clock Input to Output Delay With PLL
Symbol Description Device
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1M/-1Q -1LI -2LE
SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with PLL.
T
ICKOFPLLCC
Clock-capable clock input and
OUTFF with PLL
XC7A12T 0.83 0.83 0.83 N/A 0.83 ns
XC7A15T 0.82 0.82 0.82 N/A 0.82 1.39 ns
XC7A25T 0.83 0.83 0.83 N/A 0.83 ns
XC7A35T 0.82 0.82 0.82 N/A 0.82 1.39 ns
XC7A50T 0.82 0.82 0.82 N/A 0.82 1.39 ns
XC7A75T 0.82 0.82 0.82 N/A 0.82 1.40 ns
XC7A100T 0.82 0.82 0.82 N/A 0.82 1.40 ns
XC7A200T 0.81 0.81 0.81 N/A 0.81 1.45 ns
XA7A15T N/A 0.82 0.82 0.82 N/A N/A ns
XA7A35T N/A 0.82 0.82 0.82 N/A N/A ns
XA7A50T N/A 0.82 0.82 0.82 N/A N/A ns
XA7A75T N/A 0.82 0.82 0.82 N/A N/A ns
XA7A100T N/A 0.82 0.82 0.82 N/A N/A ns
XQ7A50T N/A 0.82 0.82 0.82 0.82 N/A ns
XQ7A100T N/A 0.82 0.82 0.82 0.82 N/A ns
XQ7A200T N/A 0.81 0.81 0.81 0.81 N/A ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2. PLL output jitter is already included in the timing calculation.
Table 43: Pin-to-Pin, Clock-to-Out using BUFIO
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1M/-1Q -1LI -2LE
SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with BUFIO.
T
ICKOFCS
Clock to out of I/O clock 5.01 5.61 6.64 6.64 6.64 7.32 ns