Datasheet

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.21) September 27, 2016 www.xilinx.com
Product Specification 42
Table 41: Clock-Capable Clock Input to Output Delay With MMCM
Symbol Description Device
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1M/-1Q -1LI -2LE
SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with MMCM.
T
ICKOFMMCMCC
Clock-capable clock input and
OUTFF with MMCM
XC7A12T 1.00 1.00 1.00 N/A 1.00 ns
XC7A15T 1.00 1.00 1.00 N/A 1.00 1.78 ns
XC7A25T 1.00 1.00 1.00 N/A 1.00 ns
XC7A35T 1.00 1.00 1.00 N/A 1.00 1.78 ns
XC7A50T 1.00 1.00 1.00 N/A 1.00 1.78 ns
XC7A75T 1.00 1.00 1.00 N/A 1.00 1.79 ns
XC7A100T 1.00 1.00 1.00 N/A 1.00 1.79 ns
XC7A200T 1.01 1.02 1.04 N/A 1.04 1.84 ns
XA7A15T N/A 1.00 1.00 1.00 N/A N/A ns
XA7A35T N/A 1.00 1.00 1.00 N/A N/A ns
XA7A50T N/A 1.00 1.00 1.00 N/A N/A ns
XA7A75T N/A 1.00 1.00 1.00 N/A N/A ns
XA7A100T N/A 1.00 1.00 1.00 N/A N/A ns
XQ7A50T N/A 1.00 1.00 1.00 1.00 N/A ns
XQ7A100T N/A 1.00 1.00 1.00 1.00 N/A ns
XQ7A200T N/A 1.02 1.04 1.04 1.04 N/A ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2. MMCM output jitter is already included in the timing calculation.