Datasheet

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.21) September 27, 2016 www.xilinx.com
Product Specification 41
Table 40: Clock-Capable Clock Input to Output Delay Without MMCM/PLL (Far Clock Region)
(1)
Symbol Description Device
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1M/-1Q -1LI -2LE
SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, without MMCM/PLL.
T
ICKOFFAR
Clock-capable clock input and OUTFF
at pins/banks farthest from the BUFGs
without MMCM/PLL (far clock region)
(2)
XC7A12T 4.97 5.55 6.44 N/A 6.44 ns
XC7A15T 5.10 5.70 6.61 N/A 6.61 7.57 ns
XC7A25T 4.97 5.55 6.44 N/A 6.44 ns
XC7A35T 5.10 5.70 6.61 N/A 6.61 7.57 ns
XC7A50T 5.10 5.70 6.61 N/A 6.61 7.57 ns
XC7A75T 5.38 6.01 7.02 N/A 7.02 7.94 ns
XC7A100T 5.38 6.01 7.02 N/A 7.02 7.94 ns
XC7A200T 6.17 6.89 8.05 N/A 8.05 9.03 ns
XA7A15T N/A 5.70 6.61 6.61 N/A N/A ns
XA7A35T N/A 5.70 6.61 6.61 N/A N/A ns
XA7A50T N/A 5.70 6.61 6.61 N/A N/A ns
XA7A75T N/A 6.01 7.02 7.02 N/A N/A ns
XA7A100T N/A 6.01 7.02 7.02 N/A N/A ns
XQ7A50T N/A 5.70 6.61 6.61 6.61 N/A ns
XQ7A100T N/A 6.01 7.02 7.02 7.02 N/A ns
XQ7A200T N/A 6.89 8.05 8.05 8.05 N/A ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Refer to the Die Level Bank Numbering Overview section of 7 Series FPGA Packaging and Pinout Specification (UG475
).