Datasheet

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.21) September 27, 2016 www.xilinx.com
Product Specification 39
PLL Switching Characteristics
Table 38: PLL Specification
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1LI -2LE
PLL_F
INMAX
Maximum input clock frequency 800.00 800.00 800.00 800.00 800.00 MHz
PLL_F
INMIN
Minimum input clock frequency 19.00 19.00 19.00 19.00 19.00 MHz
PLL_F
INJITTER
Maximum input clock period jitter < 20% of clock input period or 1 ns Max
PLL_F
INDUTY
Allowable input duty cycle: 19—49 MHz 25 25 25 25 25 %
Allowable input duty cycle: 50—199 MHz 30 30 30 30 30 %
Allowable input duty cycle: 200—399 MHz 35 35 35 35 35 %
Allowable input duty cycle: 400—499 MHz 40 40 40 40 40 %
Allowable input duty cycle: >500 MHz 45 45 45 45 45 %
PLL_F
VCOMIN
Minimum PLL VCO frequency 800.00 800.00 800.00 800.00 800.00 MHz
PLL_F
VCOMAX
Maximum PLL VCO frequency 2133.00 1866.00 1600.00 1600.00 1600.00 MHz
PLL_F
BANDWIDTH
Low PLL bandwidth at typical
(1)
1.00 1.00 1.00 1.00 1.00 MHz
High PLL bandwidth at typical
(1)
4.00 4.00 4.00 4.00 4.00 MHz
PLL_T
STATPHAOFFSET
Static phase offset of the PLL outputs
(2)
0.12 0.12 0.12 0.12 0.12 ns
PLL_T
OUTJITTER
PLL output jitter Note 3
PLL_T
OUTDUTY
PLL output clock duty-cycle precision
(4)
0.20 0.20 0.20 0.20 0.25 ns
PLL_T
LOCKMAX
PLL maximum lock time 100.00 100.00 100.00 100.00 100.00 µs
PLL_F
OUTMAX
PLL maximum output frequency 800.00 800.00 800.00 800.00 800.00 MHz
PLL_F
OUTMIN
PLL minimum output frequency
(5)
6.25 6.25 6.25 6.25 6.25 MHz
PLL_T
EXTFDVAR
External clock feedback variation < 20% of clock input period or 1 ns Max
PLL_RST
MINPULSE
Minimum reset pulse width 5.00 5.00 5.00 5.00 5.00 ns
PLL_F
PFDMAX
Maximum frequency at the phase
frequency detector
550.00 500.00 450.00 450.00 450.00 MHz
PLL_F
PFDMIN
Minimum frequency at the phase
frequency detector
19.00 19.00 19.00 19.00 19.00 MHz
PLL_T
FBDELAY
Maximum delay in the feedback path 3 ns Max or one CLKIN cycle
Dynamic Reconfiguration Port (DRP) for PLL Before and After DCLK
T
PLLDCK_DADDR
/
T
PLLCKD_DADDR
Setup and hold of D address 1.25/0.15 1.40/0.15 1.63/0.15 1.63/0.15 1.43/0.00 ns, Min
T
PLLDCK_DI
/
T
PLLCKD_DI
Setup and hold of D input 1.25/0.15 1.40/0.15 1.63/0.15 1.63/0.15 1.43/0.00 ns, Min
T
PLLDCK_DEN
/
T
PLLCKD_DEN
Setup and hold of D enable 1.76/0.00 1.97/0.00 2.29/0.00 2.29/0.00 2.40/0.00 ns, Min
T
PLLDCK_DWE
/
T
PLLCKD_DWE
Setup and hold of D write enable 1.25/0.15 1.40/0.15 1.63/0.15 1.63/0.15 1.43/0.00 ns, Min
T
PLLCKO_DRDY
CLK to out of DRDY 0.65 0.72 0.99 0.99 0.99 ns, Max