Datasheet

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.21) September 27, 2016 www.xilinx.com
Product Specification 37
MMCM Switching Characteristics
T
DCD_BUFR
Regional clock tree duty cycle
distortion
All 0.18 0.18 0.18 0.18 0.18 0.18 ns
Notes:
1. These parameters represent the worst-case duty cycle distortion observable at the I/O flip flops. For all I/O standards, IBIS can be used to
calculate any additional duty cycle distortion that might be caused by asymmetrical rise/fall times.
2. The T
CKSKEW
value represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree
skew exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx Timing Analyzer
tools to evaluate clock skew specific to your application.
Table 37: MMCM Specification
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1LI -2LE
MMCM_F
INMAX
Maximum input clock frequency 800.00 800.00 800.00 800.00 800.00 MHz
MMCM_F
INMIN
Minimum input clock frequency 10.00 10.00 10.00 10.00 10.00 MHz
MMCM_F
INJITTER
Maximum input clock period jitter < 20% of clock input period or 1 ns Max
MMCM_F
INDUTY
Allowable input duty cycle:
10—49 MHz
25 25 25 25 25 %
Allowable input duty cycle:
50—199 MHz
30 30 30 30 30 %
Allowable input duty cycle:
200—399 MHz
35 35 35 35 35 %
Allowable input duty cycle:
400—499 MHz
40 40 40 40 40 %
Allowable input duty cycle: > 500 MHz 45 45 45 45 45 %
MMCM_F
MIN_PSCLK
Minimum dynamic phase-shift clock
frequency
0.01 0.01 0.01 0.01 0.01 MHz
MMCM_F
MAX_PSCLK
Maximum dynamic phase-shift clock
frequency
550.00 500.00 450.00 450.00 450.00 MHz
MMCM_F
VCOMIN
Minimum MMCM VCO frequency 600.00 600.00 600.00 600.00 600.00 MHz
MMCM_F
VCOMAX
Maximum MMCM VCO frequency 1600.00 1440.00 1200.00 1200.00 1200.00 MHz
MMCM_F
BANDWIDTH
Low MMCM bandwidth at typical
(1)
1.00 1.00 1.00 1.00 1.00 MHz
High MMCM bandwidth at typical
(1)
4.00 4.00 4.00 4.00 4.00 MHz
MMCM_T
STATPHAOFFSET
Static phase offset of the MMCM
outputs
(2)
0.12 0.12 0.12 0.12 0.12 ns
MMCM_T
OUTJITTER
MMCM output jitter Note 3
MMCM_T
OUTDUTY
MMCM output clock duty-cycle
precision
(4)
0.20 0.20 0.20 0.20 0.25 ns
MMCM_T
LOCKMAX
MMCM maximum lock time 100.00 100.00 100.00 100.00 100.00 µs
MMCM_F
OUTMAX
MMCM maximum output frequency 800.00 800.00 800.00 800.00 800.00 MHz
MMCM_F
OUTMIN
MMCM minimum output frequency
(5)(6)
4.69 4.69 4.69 4.69 4.69 MHz
MMCM_T
EXTFDVAR
External clock feedback variation < 20% of clock input period or 1 ns Max
Table 36: Duty Cycle Distortion and Clock-Tree Skew (Cont’d)
Symbol Description Device
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1Q/-1M -1LI -2LE