Datasheet
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.21) September 27, 2016 www.xilinx.com
Product Specification 35
Clock Buffers and Networks
F
MAX_NOPIPELINEREG
Without pipeline registers
(MREG, ADREG)
260.01 227.01 190.69 190.69 190.69 150.13 MHz
F
MAX_NOPIPELINEREG_PATDET
Without pipeline registers
(MREG, ADREG) with pattern
detect
241.72 211.15 177.43 177.43 177.43 140.10 MHz
Table 32: Global Clock Switching Characteristics (Including BUFGCTRL)
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1Q/-1M -1LI -2LE
T
BCCCK_CE
/
T
BCCKC_CE
(1)
CE pins setup/hold 0.12/0.39 0.13/0.40 0.16/0.41 0.16/0.83 0.16/0.41 0.31/0.67 ns
T
BCCCK_S
/
T
BCCKC_S
(1)
S pins setup/hold 0.12/0.39 0.13/0.40 0.16/0.41 0.16/0.83 0.16/0.41 0.31/0.67 ns
T
BCCKO_O
(2)
BUFGCTRL delay from I0/I1 to O 0.08 0.09 0.10 0.10 0.10 0.14 ns
Maximum Frequency
F
MAX_BUFG
Global clock tree (BUFG) 628.00 628.00 464.00 464.00 464.00 394.00 MHz
Notes:
1. T
BCCCK_CE
and T
BCCKC_CE
must be satisfied to assure glitch-free operation of the global clock when switching between clocks. These
parameters do not apply to the BUFGMUX primitive that assures glitch-free operation. The other global clock setup and hold times are
optional; only needing to be satisfied if device operation requires simulation matches on a cycle-for-cycle basis when switching between
clocks.
2. T
BGCKO_O
(BUFG delay from I0 to O) values are the same as T
BCCKO_O
values.
Table 33: Input/Output Clock Switching Characteristics (BUFIO)
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1Q/-1M -1LI -2LE
T
BIOCKO_O
Clock to out delay from I to O 1.11 1.26 1.54 1.54 1.54 1.56 ns
Maximum Frequency
F
MAX_BUFIO
I/O clock tree (BUFIO) 680.00 680.00 600.00 600.00 600.00 600.00 MHz
Table 34: Regional Clock Buffer Switching Characteristics (BUFR)
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1Q/-1M -1LI -2LE
T
BRCKO_O
Clock to out delay from I to O 0.64 0.76 0.99 0.99 0.99 1.24 ns
T
BRCKO_O_BYP
Clock to out delay from I to O with
Divide Bypass attribute set
0.34 0.39 0.52 0.52 0.52 0.72 ns
T
BRDO_O
Propagation delay from CLR to O 0.81 0.85 1.09 1.09 1.09 0.96 ns
Table 31: DSP48E1 Switching Characteristics (Cont’d)
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1Q/-1M -1LI -2LE