Datasheet

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.21) September 27, 2016 www.xilinx.com
Product Specification 34
Clock to Outs from Output Register Clock to Output Pins
T
DSPCKO_P_PREG
CLK PREG to P output 0.33 0.37 0.44 0.44 0.44 0.54 ns
T
DSPCKO_CARRYCASCOUT_PREG
CLK PREG to
CARRYCASCOUT output
0.52 0.59 0.69 0.69 0.69 0.84 ns
Clock to Outs from Pipeline Register Clock to Output Pins
T
DSPCKO_P_MREG
CLK MREG to P output 1.68 1.93 2.31 2.31 2.31 2.73 ns
T
DSPCKO_CARRYCASCOUT_MREG
CLK MREG to
CARRYCASCOUT output
1.92 2.21 2.64 2.64 2.64 3.12 ns
T
DSPCKO_P_ADREG_MULT
CLK ADREG to P output using
multiplier
2.72 3.10 3.69 3.69 3.69 4.60 ns
T
DSPCKO_CARRYCASCOUT_ADREG_
MULT
CLK ADREG to
CARRYCASCOUT output using
multiplier
2.96 3.38 4.02 4.02 4.02 4.99 ns
Clock to Outs from Input Register Clock to Output Pins
T
DSPCKO_P_AREG_MULT
CLK AREG to P output using
multiplier
3.94 4.51 5.37 5.37 5.37 6.84 ns
T
DSPCKO_P_BREG
CLK BREG to P output not using
multiplier
1.64 1.87 2.22 2.22 2.22 2.65 ns
T
DSPCKO_P_CREG
CLK CREG to P output not
using multiplier
1.69 1.93 2.30 2.30 2.30 2.81 ns
T
DSPCKO_P_DREG_MULT
CLK DREG to P output using
multiplier
3.91 4.48 5.32 5.32 5.32 6.77 ns
Clock to Outs from Input Register Clock to Cascading Output Pins
T
DSPCKO_{ACOUT; BCOUT}_{AREG;
BREG}
CLK (ACOUT, BCOUT) to {A,B}
register output
0.64 0.73 0.87 0.87 0.87 1.02 ns
T
DSPCKO_CARRYCASCOUT_{AREG,
BREG}_MULT
CLK (AREG, BREG) to
CARRYCASCOUT output using
multiplier
4.19 4.79 5.70 5.70 5.70 7.24 ns
T
DSPCKO_CARRYCASCOUT_ BREG
CLK BREG to
CARRYCASCOUT output not
using multiplier
1.88 2.15 2.55 2.55 2.55 3.04 ns
T
DSPCKO_CARRYCASCOUT_
DREG_MULT
CLK DREG to
CARRYCASCOUT output using
multiplier
4.16 4.76 5.65 5.65 5.65 7.17 ns
T
DSPCKO_CARRYCASCOUT_ CREG
CLK CREG to
CARRYCASCOUT output
1.94 2.21 2.63 2.63 2.63 3.20 ns
Maximum Frequency
F
MAX
With all registers used 628.93 550.66 464.25 464.25 464.25 363.77 MHz
F
MAX_PATDET
With pattern detector 531.63 465.77 392.93 392.93 392.93 310.08 MHz
F
MAX_MULT_NOMREG
Two register multiply without
MREG
349.28 305.62 257.47 257.47 257.47 210.44 MHz
F
MAX_MULT_NOMREG_PATDET
Two register multiply without
MREG with pattern detect
317.26 277.62 233.92 233.92 233.92 191.28 MHz
F
MAX_PREADD_MULT_NOADREG
Without ADREG 397.30 346.26 290.44 290.44 290.44 223.26 MHz
F
MAX_PREADD_MULT_NOADREG_
PATDET
Without ADREG with pattern
detect
397.30 346.26 290.44 290.44 290.44 223.26 MHz
Table 31: DSP48E1 Switching Characteristics (Cont’d)
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1Q/-1M -1LI -2LE