Datasheet

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.21) September 27, 2016 www.xilinx.com
Product Specification 32
DSP48E1 Switching Characteristics
Table 31: DSP48E1 Switching Characteristics
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1Q/-1M -1LI -2LE
Setup and Hold Times of Data/Control Pins to the Input Register Clock
T
DSPDCK_A_AREG
/
T
DSPCKD_A_AREG
A input to A register CLK 0.26/
0.12
0.30/
0.13
0.37/
0.14
0.37/
0.28
0.37/
0.14
0.45/
0.14
ns
T
DSPDCK_B_BREG
/
T
DSPCKD_B_BREG
B input to B register CLK 0.33/
0.15
0.38/
0.16
0.45/
0.18
0.45/
0.25
0.45/
0.18
0.60/
0.19
ns
T
DSPDCK_C_CREG
/
T
DSPCKD_C_CREG
C input to C register CLK 0.17/
0.17
0.20/
0.19
0.24/
0.21
0.24/
0.26
0.24/
0.21
0.34/
0.29
ns
T
DSPDCK_D_DREG
/
T
DSPCKD_D_DREG
D input to D register CLK 0.25/
0.25
0.32/
0.27
0.42/
0.27
0.42/
0.42
0.42/
0.27
0.54/
0.23
ns
T
DSPDCK_ACIN_AREG
/
T
DSPCKD_ACIN_AREG
ACIN input to A register CLK 0.23/
0.12
0.27/
0.13
0.32/
0.14
0.32/
0.17
0.32/
0.14
0.36/
0.14
ns
T
DSPDCK_BCIN_BREG
/
T
DSPCKD_BCIN_BREG
BCIN input to B register CLK 0.25/
0.15
0.29/
0.16
0.36/
0.18
0.36/
0.18
0.36/
0.18
0.41/
0.19
ns
Setup and Hold Times of Data Pins to the Pipeline Register Clock
T
DSPDCK_
{
A, B
}
_MREG_MULT
/
T
DSPCKD_{A, B}_MREG_MULT
{A, B} input to M register CLK
using multiplier
2.40/
–0.01
2.76/
–0.01
3.29/
–0.01
3.29/
–0.01
3.29/
–0.01
4.31/
–0.07
ns
T
DSPDCK_
{
A, D
}
_ADREG
/
T
DSPCKD_{A, D}_ADREG
{A, D} input to AD register CLK 1.29/
–0.02
1.48/
–0.02
1.76/
–0.02
1.76/
–0.02
1.76/
–0.02
2.29/
–0.27
ns
Setup and Hold Times of Data/Control Pins to the Output Register Clock
T
DSPDCK_{A, B}_PREG_MULT
/
T
DSPCKD_{A, B} _PREG_MULT
{A, B} input to P register CLK
using multiplier
4.02/
–0.28
4.60/
–0.28
5.48/
–0.28
5.48/
–0.28
5.48/
–0.28
6.95/
–0.48
ns
T
DSPDCK_D_PREG_MULT
/
T
DSPCKD_D_PREG_MULT
D input to P register CLK using
multiplier
3.93/
–0.73
4.50/
–0.73
5.35/
–0.73
5.35/
–0.73
5.35/
–0.73
6.73/
–1.68
ns
T
DSPDCK_{A, B} _PREG
/
T
DSPCKD_{A, B} _PREG
A or B input to P register CLK
not using multiplier
1.73/
–0.28
1.98/
–0.28
2.35/
–0.28
2.35/
–0.28
2.35/
–0.28
2.80/
–0.48
ns
T
DSPDCK_C_PREG
/
T
DSPCKD_C_PREG
C input to P register CLK not
using multiplier
1.54/
–0.26
1.76/
–0.26
2.10/
–0.26
2.10/
–0.26
2.10/
–0.26
2.54/
–0.45
ns
T
DSPDCK_PCIN_PREG
/
T
DSPCKD_PCIN_PREG
PCIN input to P register CLK 1.32/
–0.15
1.51/
–0.15
1.80/
–0.15
1.80/
–0.15
1.80/
–0.15
2.13/
–0.25
ns
Setup and Hold Times of the CE Pins
T
DSPDCK_{CEA;CEB}_{AREG;BREG}
/
T
DSPCKD_{CEA;CEB}_{AREG;BREG}
{CEA; CEB} input to {A; B}
register CLK
0.35/
0.06
0.42/
0.08
0.52/
0.11
0.52/
0.11
0.52/
0.11
0.64/
0.11
ns
T
DSPDCK_CEC_CREG
/
T
DSPCKD_CEC_CREG
CEC input to C register CLK 0.28/
0.10
0.34/
0.11
0.42/
0.13
0.42/
0.13
0.42/
0.13
0.49/
0.16
ns
T
DSPDCK_CED_DREG
/
T
DSPCKD_CED_DREG
CED input to D register CLK 0.36/
–0.03
0.43/
–0.03
0.52/
–0.03
0.52/
–0.03
0.52/
–0.03
0.68/
0.14
ns
T
DSPDCK_CEM_MREG
/
T
DSPCKD_CEM_MREG
CEM input to M register CLK 0.17/
0.18
0.21/
0.20
0.27/
0.23
0.27/
0.23
0.27/
0.23
0.45/
0.29
ns
T
DSPDCK_CEP_PREG
/
T
DSPCKD_CEP_PREG
CEP input to P register CLK 0.36/
0.01
0.43/
0.01
0.53/
0.01
0.53/
0.01
0.53/
0.01
0.63/
0.00
ns