Datasheet

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.21) September 27, 2016 www.xilinx.com
Product Specification 30
T
RDCK_DI_ECC
/
T
RCKD_DI_ECC
DIN inputs with block RAM
ECC in standard mode
(9)
0.50/0.43 0.55/0.46 0.63/0.50 0.63/0.50 0.63/0.50 0.78/0.54 ns, Min
T
RDCK_DI_ECCW
/
T
RCKD_DI_ECCW
DIN inputs with block RAM
ECC encode only
(9)
0.93/0.43 1.02/0.46 1.17/0.50 1.17/0.50 1.17/0.50 1.38/0.48 ns, Min
T
RDCK_DI_ECC_FIFO
/
T
RCKD_DI_ECC_FIFO
DIN inputs with FIFO ECC
in standard mode
(9)
1.04/0.56 1.15/0.59 1.32/0.64 1.32/0.64 1.32/0.64 1.55/0.77 ns, Min
T
RCCK_INJECTBITERR
/
T
RCKC_INJECTBITERR
Inject single/double bit
error in ECC mode
0.58/0.35 0.64/0.37 0.74/0.40 0.74/0.52 0.74/0.40 0.92/0.48 ns, Min
T
RCCK_EN
/T
RCKC_EN
Block RAM enable (EN)
input
0.35/0.20 0.39/0.21 0.45/0.23 0.45/0.41 0.45/0.23 0.57/0.26 ns, Min
T
RCCK_REGCE
/
T
RCKC_REGCE
CE input of output register 0.24/0.15 0.29/0.15 0.36/0.16 0.36/0.39 0.36/0.16 0.40/0.19 ns, Min
T
RCCK_RSTREG
/
T
RCKC_RSTREG
Synchronous RSTREG
input
0.29/0.07 0.32/0.07 0.35/0.07 0.35/0.17 0.35/0.07 0.41/0.07 ns, Min
T
RCCK_RSTRAM
/
T
RCKC_RSTRAM
Synchronous RSTRAM
input
0.32/0.42 0.34/0.43 0.36/0.46 0.36/0.57 0.36/0.46 0.40/0.47 ns, Min
T
RCCK_WEA
/
T
RCKC_WEA
Write enable (WE) input
(block RAM only)
0.44/0.18 0.48/0.19 0.54/0.20 0.54/0.42 0.54/0.20 0.64/0.23 ns, Min
T
RCCK_WREN
/
T
RCKC_WREN
WREN FIFO inputs 0.46/0.30 0.46/0.35 0.47/0.43 0.47/0.43 0.47/0.43 0.77/0.44 ns, Min
T
RCCK_RDEN
/
T
RCKC_RDEN
RDEN FIFO inputs 0.42/0.30 0.43/0.35 0.43/0.43 0.43/0.62 0.43/0.43 0.71/0.50 ns, Min
Reset Delays
T
RCO_FLAGS
Reset RST to FIFO
flags/pointers
(10)
0.90 0.98 1.10 1.10 1.10 1.25 ns, Max
T
RREC_RST
/
T
RREM_RST
FIFO reset recovery and
removal timing
(11)
1.87/–0.81 2.07/–0.81 2.37/–0.81 2.37/–0.58 2.37/–0.81 2.44/–0.71 ns, Max
Maximum Frequency
F
MAX_BRAM_WF_NC
Block RAM (write first and
no change modes) when
not in SDP RF mode
509.68 460.83 388.20 388.20 388.20 315.66 MHz
F
MAX_BRAM_RF_
PERFORMANCE
Block RAM (read first,
performance mode) when
in SDP RF mode but no
address overlap between
port A and port B
509.68 460.83 388.20 388.20 388.20 315.66 MHz
F
MAX_BRAM_RF_
DELAYED_WRITE
Block RAM (read first,
delayed write mode) when
in SDP RF mode and
there is possibility of
overlap between port A
and port B addresses
447.63 404.53 339.67 339.67 339.67 268.96 MHz
Table 30: Block RAM and FIFO Switching Characteristics (Cont’d)
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1Q/-1M -1LI -2LE