Datasheet

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.21) September 27, 2016 www.xilinx.com
Product Specification 29
Block RAM and FIFO Switching Characteristics
Table 30: Block RAM and FIFO Switching Characteristics
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1Q/-1M -1LI -2LE
Block RAM and FIFO Clock-to-Out Delays
T
RCKO_DO
and
T
RCKO_DO_REG
(1)
Clock CLK to DOUT
output (without output
register)
(2)(3)
1.85 2.13 2.46 2.46 2.46 2.87 ns, Max
Clock CLK to DOUT
output (with output
register)
(4)(5)
0.64 0.74 0.89 0.89 0.89 1.02 ns, Max
T
RCKO_DO_ECC
and
T
RCKO_DO_ECC_REG
Clock CLK to DOUT
output with ECC (without
output register)
(2)(3)
2.77 3.04 3.84 3.84 3.84 5.30 ns, Max
Clock CLK to DOUT
output with ECC (with
output register)
(4)(5)
0.73 0.81 0.94 0.94 0.94 1.11 ns, Max
T
RCKO_DO_CASCOUT
and
T
RCKO_DO_CASCOUT_REG
Clock CLK to DOUT
output with cascade
(without output register)
(2)
2.61 2.88 3.30 3.30 3.30 3.76 ns, Max
Clock CLK to DOUT
output with cascade (with
output register)
(4)
1.16 1.28 1.46 1.46 1.46 1.56 ns, Max
T
RCKO_FLAGS
Clock CLK to FIFO flags
outputs
(6)
0.76 0.87 1.05 1.05 1.05 1.14 ns, Max
T
RCKO_POINTERS
Clock CLK to FIFO
pointers outputs
(7)
0.94 1.02 1.15 1.15 1.15 1.30 ns, Max
T
RCKO_PARITY_ECC
Clock CLK to ECCPARITY
in ECC encode only mode
0.78 0.85 0.94 0.94 0.94 1.10 ns, Max
T
RCKO_SDBIT_ECC
and
T
RCKO_SDBIT_ECC_REG
Clock CLK to BITERR
(without output register)
2.56 2.81 3.55 3.55 3.55 4.90 ns, Max
Clock CLK to BITERR
(with output register)
0.68 0.76 0.89 0.89 0.89 1.05 ns, Max
T
RCKO_RDADDR_ECC
and
T
RCKO_RDADDR_ECC_REG
Clock CLK to RDADDR
output with ECC (without
output register)
0.75 0.88 1.07 1.07 1.07 1.15 ns, Max
Clock CLK to RDADDR
output with ECC (with
output register)
0.84 0.93 1.08 1.08 1.08 1.29 ns, Max
Setup and Hold Times Before/After Clock CLK
T
RCCK_ADDRA
/
T
RCKC_ADDRA
ADDR inputs
(8)
0.45/0.31 0.49/0.33 0.57/0.36 0.57/0.52 0.57/0.36 0.77/0.45 ns, Min
T
RDCK_DI_WF_NC
/
T
RCKD_DI_WF_NC
Data input setup/hold time
when block RAM is
configured in
WRITE_FIRST or
NO_CHANGE mode
(9)
0.58/0.60 0.65/0.63 0.74/0.67 0.74/0.67 0.74/0.67 0.92/0.76 ns, Min
T
RDCK_DI_RF
/
T
RCKD_DI_RF
Data input setup/hold time
when block RAM is
configured in
READ_FIRST mode
(9)
0.20/0.29 0.22/0.34 0.25/0.41 0.25/0.50 0.25/0.41 0.29/0.38 ns, Min