Datasheet
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.21) September 27, 2016 www.xilinx.com
Product Specification 28
CLB Distributed RAM Switching Characteristics (SLICEM Only)
CLB Shift Register Switching Characteristics (SLICEM Only)
Table 28: CLB Distributed RAM Switching Characteristics
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1Q/-1M -1LI -2LE
Sequential Delays
T
SHCKO
Clock to A – B outputs 0.98 1.09 1.32 1.32 1.32 1.54 ns, Max
T
SHCKO_1
Clock to AMUX – BMUX outputs 1.37 1.53 1.86 1.86 1.86 2.18 ns, Max
Setup and Hold Times Before/After Clock CLK
T
DS_LRAM
/
T
DH_LRAM
A – D inputs to CLK 0.54/0.28 0.60/0.30 0.72/0.35 0.72/0.37 0.72/0.35 0.96/0.40 ns, Min
T
AS_LRAM
/
T
AH_LRAM
Address An inputs to clock 0.27/0.55 0.30/0.60 0.37/0.70 0.37/0.71 0.37/0.70 0.43/0.71 ns, Min
Address An inputs through MUXs
and/or carry logic to clock
0.69/0.18 0.77/0.21 0.94/0.26 0.94/0.35 0.94/0.26 1.11/0.31 ns, Min
T
WS_LRAM
/
T
WH_LRAM
WE input to clock 0.38/0.10 0.43/0.12 0.53/0.17 0.53/0.17 0.53/0.17 0.62/0.13 ns, Min
T
CECK_LRAM
/
T
CKCE_LRAM
CE input to CLK 0.39/0.10 0.44/0.11 0.53/0.17 0.53/0.17 0.53/0.17 0.63/0.12 ns, Min
Clock CLK
T
MPW_LRAM
Minimum pulse width 1.05 1.131.251.251.251.61ns, Min
T
MCP
Minimum clock period 2.10 2.26 2.50 2.50 2.50 3.21 ns, Min
Notes:
1. T
SHCKO
also represents the CLK to XMUX output. Refer to the timing report for the CLK to XMUX path.
Table 29: CLB Shift Register Switching Characteristics
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1Q/-1M -1LI -2LE
Sequential Delays
T
REG
Clock to A – D outputs 1.19 1.33 1.61 1.61 1.61 1.89 ns, Max
T
REG_MUX
Clock to AMUX – DMUX output 1.58 1.77 2.15 2.15 2.15 2.53 ns, Max
T
REG_M31
Clock to DMUX output via M31
output
1.12 1.23 1.46 1.46 1.46 1.68 ns, Max
Setup and Hold Times Before/After Clock CLK
T
WS_SHFREG
/
T
WH_SHFREG
WE input
0.37/0.10 0.41/0.12 0.51/0.17 0.51/0.17 0.51/0.17
0.59/0.13 ns, Min
T
CECK_SHFREG
/
T
CKCE_SHFREG
CE input to CLK
0.37/0.10 0.42/0.11 0.52/0.17 0.52/0.17 0.52/0.17
0.60/0.12 ns, Min
T
DS_SHFREG
/
T
DH_SHFREG
A – D inputs to CLK
0.33/0.34 0.37/0.37 0.44/0.43 0.44/0.44 0.44/0.43
0.54/0.55 ns, Min
Clock CLK
T
MPW_SHFREG
Minimum pulse width 0.77 0.86 0.98 0.98 0.98 1.22 ns, Min