Datasheet
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.21) September 27, 2016 www.xilinx.com
Product Specification 25
Input/Output Delay Switching Characteristics
Table 25: Input/Output Delay Switching Characteristics
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1Q/-1M -1LI -2LE
IDELAYCTRL
T
DLYCCO_RDY
Reset to ready for IDELAYCTRL 3.67 3.67 3.67 3.67 3.67 3.67 µs
F
IDELAYCTRL_REF
Attribute REFCLK
frequency = 200.00
(1)
200.00 200.00 200.00 200.00 200.00 200.00 MHz
Attribute REFCLK
frequency = 300.00
(1)
300.00 300.00 300.00 300.00 300.00 300.00 MHz
Attribute REFCLK
frequency = 400.00
(1)
400.00 400.00 N/A N/A N/A N/A MHz
IDELAYCTRL_REF_
PRECISION
REFCLK precision ±10 ±10 ±10 ±10 ±10 ±10 MHz
T
IDELAYCTRL_RPW
Minimum Reset pulse width 59.28 59.28 59.28 59.28 59.28 59.28 ns
IDELAY
T
IDELAYRESOLUTION
IDELAY chain delay resolution 1/(32 x 2 x F
REF
)ps
T
IDELAYPAT_JIT
Pattern dependent period jitter in
delay chain for clock pattern.
(2)
000000ps
per tap
Pattern dependent period jitter in
delay chain for random data
pattern (PRBS 23)
(3)
±5 ±5 ±5 ±5 ±5 ±5 ps
per tap
Pattern dependent period jitter in
delay chain for random data
pattern (PRBS 23)
(4)
±9 ±9 ±9 ±9 ±9 ±9 ps
per tap
T
IDELAY_CLK_MAX
Maximum frequency of CLK input
to IDELAY
680.00 680.00 600.00 600.00 600.00 520.00 MHz
T
IDCCK_CE
/
T
IDCKC_CE
CE pin setup/hold with respect to
C for IDELAY
0.12/0.11 0.16/0.13 0.21/0.16 0.21/0.16 0.21/0.16 0.14/0.16 ns
T
IDCCK_INC
/
T
IDCKC_INC
INC pin setup/hold with respect to
C for IDELAY
0.12/0.16 0.14/0.18 0.16/0.22 0.16/0.23 0.16/0.22 0.10/0.23 ns
T
IDCCK_RST
/
T
IDCKC_RST
RST pin setup/hold with respect
to C for IDELAY
0.15/0.09 0.16/0.11 0.18/0.14 0.18/0.14 0.18/0.14 0.22/0.19 ns
T
IDDO_IDATAIN
Propagation delay through
IDELAY
Note 5 Note 5 Note 5 Note 5 Note 5 Note 5 ps
Notes:
1. Average Tap Delay at 200 MHz = 78 ps, at 300 MHz = 52 ps, and at 400 MHz = 39 ps.
2. When HIGH_PERFORMANCE mode is set to TRUE or FALSE.
3. When HIGH_PERFORMANCE mode is set to TRUE.
4. When HIGH_PERFORMANCE mode is set to FALSE.
5. Delay depends on IDELAY tap setting. See the timing report for actual values.