Datasheet

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.21) September 27, 2016 www.xilinx.com
Product Specification 24
Output Serializer/Deserializer Switching Characteristics
Table 24: OSERDES Switching Characteristics
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1Q/-1M -1LI -2LE
Setup/Hold
T
OSDCK_D
/
T
OSCKD_D
D input setup/hold with respect to
CLKDIV
0.42/0.03 0.45/0.03 0.63/0.03 0.63/0.08 0.63/0.03 0.44/–0.02 ns
T
OSDCK_T
/
T
OSCKD_T
(1)
T input setup/hold with respect to
CLK
0.69/–0.13 0.73/–0.13 0.88/–0.13 0.88/–0.13 0.88/–0.13 0.66/–0.25 ns
T
OSDCK_T2
/
T
OSCKD_T2
(1)
T input setup/hold with respect to
CLKDIV
0.31/–0.13 0.34/–0.13 0.39/–0.13 0.39/–0.13 0.39/–0.13 0.46/–0.25 ns
T
OSCCK_OCE
/
T
OSCKC_OCE
OCE input setup/hold with respect
to CLK
0.32/0.58 0.34/0.58 0.51/0.58 0.51/0.58 0.51/0.58 0.28/–0.04 ns
T
OSCCK_S
SR (reset) input setup with respect
to CLKDIV
0.47 0.52 0.85 0.85 0.85 0.70 ns
T
OSCCK_TCE
/
T
OSCKC_TCE
TCE input setup/hold with respect
to CLK
0.32/0.01 0.34/0.01 0.51/0.01 0.51/0.10 0.51/0.01 0.24/0.00 ns
Sequential Delays
T
OSCKO_OQ
Clock to out from CLK to OQ 0.40 0.42 0.48 0.48 0.48 0.54 ns
T
OSCKO_TQ
Clock to out from CLK to TQ 0.47 0.49 0.56 0.56 0.56 0.63 ns
Combinatorial
T
OSDO_TTQ
T input to TQ Out 0.83 0.92 1.11 1.11 1.11 1.18 ns
Notes:
1. T
OSDCK_T2
and T
OSCKD_T2
are reported as T
OSDCK_T
/T
OSCKD_T
in the timing report.