Datasheet
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.21) September 27, 2016 www.xilinx.com
Product Specification 23
Input Serializer/Deserializer Switching Characteristics
Combinatorial
T
ODQ
D1 to OQ out or T1 to TQ out 0.83 0.96 1.16 1.16 1.16 1.36 ns
Sequential Delays
T
OCKQ
CLK to OQ/TQ out 0.47 0.49 0.56 0.56 0.56 0.63 ns
T
RQ_OLOGIC
SR pin to OQ/TQ out 0.72 0.80 0.95 0.95 0.95 1.12 ns
T
GSRQ_OLOGIC
Global set/reset to Q outputs 7.60 7.60 10.51 10.51 10.51 11.39 ns
Set/Reset
T
RPW_OLOGIC
Minimum pulse width, SR inputs 0.64 0.74 0.74 0.74 0.74 0.74 ns,
Min
Table 23: ISERDES Switching Characteristics
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1Q/-1M -1LI -2LE
Setup/Hold for Control Lines
T
ISCCK_BITSLIP
/
T
ISCKC_BITSLIP
BITSLIP pin setup/hold with
respect to CLKDIV
0.01/0.14 0.02/0.15 0.02/0.17 0.02/0.17 0.02/0.17 0.02/0.21 ns
T
ISCCK_CE
/
T
ISCKC_CE
(2)
CE pin setup/hold with respect to
CLK (for CE1)
0.45/–0.01 0.50/–0.01 0.72/–0.01 0.72/–0.01 0.72/–0.01 0.45/–0.11 ns
T
ISCCK_CE2
/
T
ISCKC_CE2
(2)
CE pin setup/hold with respect to
CLKDIV (for CE2)
–0.10/0.33 –0.10/0.36 –0.10/0.40 –0.10/0.40 –0.10/0.40 –0.17/0.40 ns
Setup/Hold for Data Lines
T
ISDCK_D
/
T
ISCKD_D
D pin setup/hold with respect to
CLK
–0.02/0.12 –0.02/0.14 –0.02/0.17 –0.02/0.17 –0.02/0.17 –0.04/0.19 ns
T
ISDCK_DDLY
/
T
ISCKD_DDLY
DDLY pin setup/hold with respect
to CLK (using IDELAY)
(1)
–0.02/0.12 –0.02/0.14 –0.02/0.17 –0.02/0.17 –0.02/0.17 –0.03/0.19 ns
T
ISDCK_D_DDR
/
T
ISCKD_D_DDR
D pin setup/hold with respect to
CLK at DDR mode
–0.02/0.12 –0.02/0.14 –0.02/0.17 –0.02/0.17 –0.02/0.17 –0.04/0.19 ns
T
ISDCK_DDLY_DDR
/
T
ISCKD_DDLY_DDR
D pin setup/hold with respect to
CLK at DDR mode (using
IDELAY)
(1)
0.12/0.12 0.14/0.14 0.17/0.17 0.17/0.17 0.17/0.17 0.19/0.19 ns
Sequential Delays
T
ISCKO_Q
CLKDIV to out at Q pin 0.53 0.54 0.66 0.66 0.66 0.67 ns
Propagation Delays
T
ISDO_DO
D input to DO output pin 0.11 0.11 0.13 0.13 0.13 0.14 ns
Notes:
1. Recorded at 0 tap value.
2. T
ISCCK_CE2
and T
ISCKC_CE2
are reported as T
ISCCK_CE
/T
ISCKC_CE
in the timing report.
Table 22: OLOGIC Switching Characteristics (Cont’d)
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1Q/-1M -1LI -2LE