Datasheet
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.21) September 27, 2016 www.xilinx.com
Product Specification 22
Input/Output Logic Switching Characteristics
Table 21: ILOGIC Switching Characteristics
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1Q/-1M -1LI -2LE
Setup/Hold
T
ICE1CK
/
T
ICKCE1
CE1 pin setup/hold with respect to
CLK
0.48/0.02 0.54/0.02 0.76/0.02 0.76/0.02 0.76/0.02 0.50/–0.07 ns
T
ISRCK
/
T
ICKSR
SR pin setup/hold with respect to
CLK
0.60/0.01 0.70/0.01 1.13/0.01 1.13/0.01 1.13/0.01 0.88/–0.35 ns
T
IDOCK
/
T
IOCKD
D pin setup/hold with respect to CLK
without Delay
0.01/0.27 0.01/0.29 0.01/0.33 0.01/0.33 0.01/0.33 0.01/0.33 ns
T
IDOCKD
/
T
IOCKDD
DDLY pin setup/hold with respect to
CLK (using IDELAY)
0.02/0.27 0.02/0.29 0.02/0.33 0.02/0.33 0.02/0.33 0.01/0.33 ns
Combinatorial
T
IDI
D pin to O pin propagation delay, no
Delay
0.11 0.11 0.13 0.13 0.13 0.14 ns
T
IDID
DDLY pin to O pin propagation delay
(using IDELAY)
0.11 0.12 0.14 0.14 0.14 0.15 ns
Sequential Delays
T
IDLO
D pin to Q1 pin using flip-flop as a
latch without Delay
0.41 0.44 0.51 0.51 0.51 0.54 ns
T
IDLOD
DDLY pin to Q1 pin using flip-flop as
a latch (using IDELAY)
0.41 0.44 0.51 0.51 0.51 0.55 ns
T
ICKQ
CLK to Q outputs 0.53 0.57 0.66 0.66 0.66 0.71 ns
T
RQ_
ILOGIC
SR pin to OQ/TQ out 0.96 1.08 1.32 1.32 1.32 1.32 ns
T
GSRQ_
ILOGIC
Global set/reset to Q outputs 7.60 7.60 10.51 10.51 10.51 11.39 ns
Set/Reset
T
RPW_
ILOGIC
Minimum pulse width, SR inputs 0.61 0.72 0.72 0.72 0.72 0.72 ns, Min
Table 22: OLOGIC Switching Characteristics
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1Q/-1M -1LI -2LE
Setup/Hold
T
ODCK
/
T
OCKD
D1/D2 pins setup/hold with respect
to CLK
0.67/–0.11 0.71/–0.11 0.84/–0.11 0.84/–0.06 0.84/–0.11 0.64/0.03 ns
T
OOCECK
/
T
OCKOCE
OCE pin setup/hold with respect to
CLK
0.32/0.58 0.34/0.58 0.51/0.58 0.51/0.58 0.51/0.58 0.28/0.01 ns
T
OSRCK
/
T
OCKSR
SR pin setup/hold with respect to
CLK
0.37/0.21 0.44/0.21 0.80/0.21 0.80/0.21 0.80/0.21 0.62/–0.25 ns
T
OTCK
/
T
OCKT
T1/T2 pins setup/hold with respect to
CLK
0.69/–0.14 0.73/–0.14 0.89/–0.14 0.89/–0.11 0.89/–0.14 0.66/0.02 ns
T
OTCECK
/
T
OCKTCE
TCE pin setup/hold with respect to
CLK
0.32/0.01 0.34/0.01 0.51/0.01 0.51/0.10 0.51/0.01 0.24/0.05 ns